VHDL to CLAy

Synthesizing VHDL to CLAy

Introduction

Given a knowledge of SYNOPSYS Design Analyzer and the CLAy tools, this page will lead you through the steps required to synthesize your VHDL and auto-place-and-route it for the CLAy FPGA. This is not really a tutorial but rather just a listing of the steps required.

Setting Up Your Account

  1. Make sure that the CLAy tools are on your search path in your .cshrc file. The CLAy tools are found in: /sun_data/clay/1.10/bin
  2. Make a subdirectory off your CLAy area for your new design. Your CLAy area is the directory where your "cli.ini" file is located.
  3. Update your "cli.ini" file to point to the new design directory.
  4. Copy the file "design.cfg" to the new design subdirectory.
  5. Copy the file "/sun_data/clay/1.10/lib/synopsys/wv_ct_synopsys_setup" into the new design subdirectory and call it ".synopsys_dc.setup". This will override the settings in your main ".synopsys_dc.setup" file in home directory.
  6. Update the following settings in the file: design, company, and search path to match the installation.
For example, here are the commands I would use to do the steps above, after having fixed my search path to include the CLAy tools: mkdir ~/cli/synth <edit "cli.ini" to point to ./synth> cp ~/cli/design.cfg ~/cli/synth cp /sun_data/clay/1.10/lib/synopsys/wv_ct_synopsys_setup \ ~/cli/synth/.synopsys_dc.setup <edit ~/cli/synth/.synopsys_dc.setup and customize> Here is the top portion of my "~/cli/synth/.synopsys_dc.setup" file: designer="Brent Nelson"; company = "BYU"; search_path = {"." "/sun_data/clay/1.10/lib/synopsys" "/fpga3/cad/synopsys/libraries/syn" };

Do Your VHDL Design

Do whatever design you desire. Make sure the name of your top level entity is the same as the name of your synthesis subdirectory.

Synthesize Your Design

Run design_analyzer and "Read..." and then "Optimize..." your VHDL design. Be sure you are in the synthesis subdirectory when you start design_analyzer so that the ".synopsys_dc.setup" file will be read.

At the current time there are no predefined wire load files or the like for the optimization - just use whatever defaults you get. Once that is done, you should "Save As..." your design as a VERILOG file. Use a ".ver" extension for the file name.

Because of the way the CLAy tools work and overwrite your original design in the following steps, you should make a backup copy of the VERILOG file at this point.

Assign Pins to Your Ports

Any port at the top level will be assigned to a pin on the chip. You may either assign the pins yourself interactively or you may let the auto-place-and-route tools do it for you.

Manual Pin Placement

After starting up the ct program, use Netlist->Pin Assignment to enter the interactive pin placement program. On the left of the screen are the top-level ports of your design. Also there is a pull-down box with the various buffer types. Using these and the mouse, you may assign your ports to any package pins you desire.

You may choose to assign your clock and reset signals to the global signals rather than to user I/O pins. This is done with the Port->Assign Global Clock and the Port->Assign Global Reset menu items.

When you are done with your pin placement you may save this information in a file with a ".ios" extension using the Manager->Save menu item.

The final step is to actually update the VERILOG netlist with the pin placement information. This is done using the Netlist->Update Verilog Netlist menu item. This will add an extra level of heirarchy to the VERILOG netlist file which contains the pins assignments you have made at the top level of the hierarchy. This will change your VERILOG file. Thus, after doing this step, if you wish to go back and start over, you will need to use the backup copy of the VERILOG file that you created earlier.

You may leave the pin assignment program now using Manager->Exit.

Auto Pin Placement

If you would rather, you may let the auto-place-and-route tools do the pin placement for you. The only step you need to perform is to add the new level of hierarchy around your design. This is done by executing the programs iosgen -g and ioprep -q on your design in an xterm window. This accomplishes the same thing as the last step in the Manual Pin Placement instructions above.

Read In The VERILOG Netlist

You now read in the VERILOG netlist and convert it to a CDB file. Do this with the Netlist->VERILOG->CDB Netlist menu command. You may choose with this to ignore the specific pin placement you did above or to use it.

Automatic Place and Route

At this point you may execute Layout->Auto P&R to do the layout. If all succeeds you may view the results using Interact. If not, you need to go to another set of instructions to figure out why.
Updated 29 May 1995.
Brent Nelson (nelson@ee.byu.edu)