BYU TERAMAC Tutorial
The TERAMAC machine from HP labs has previously been programmed via
the graphical schematic entry program Tsutsuji. At BYU I have
created a VHDL environment as an alternative. Using
it you can synthesize VHDL to a netlist file suitable for use
by the TERAMAC compiler.
This manual covers design and synthesis of VHDL for TERAMAC using
the SYNOPSYS tools as well as execution of those designs on
TERAMAC. However, if you are doing Tsutsuji-based design, you
can still benefit from this tutorial in that you can begin at the
"tc" stage of compilation and follow along with the final stages
of the examples to understand how to execute your design on TERAMAC.
Doing your design using VHDL provides
a number of useful things:
- accurate simulation of multi-ported memory and register file
blocks
- simulation support for memory initialization
- simulation of the TERAMAC environment to model interactive
execution
At the current time the examples listed exist in
"/fpga3/cad/tmac/demos" at BYU.
Table of Contents:
Last updated: 13 December 1995
Brent Nelson
nelson@ee.byu.edu