library ieee;
use ieee.std_logic_1164.all;

------------------------------------------------------------------------------
-- The top level system entity
entity tmac is
end tmac;

------------------------------------------------------------------------------
-- A blank architecture
architecture simulate of tmac is

  -- The breakpoint signals
  signal BREAKPOINT_NOT    :  std_ulogic := '1';

  -- The reset signal
  signal reset : std_ulogic := '1';


  -- The signal name of 'clk' is important to the netlister tools.
  -- Don't change it.
  signal clk : std_ulogic := '1';

  -- The user's part
  component DEBUG 
    port(
	 clk : in std_ulogic;
	 reset : in std_ulogic;
	 BREAKPOINT_NOT : out std_ulogic
	 );
  end component;
--  for all:DEBUG use entity WORK.memcpy(archBody);
  
begin

  -- The clock waveform.  The frequency is immaterial.
  clk <=not(clk) after 5 ns;

  -- The user's design instantiation
  USER:DEBUG port map(
		      clk => clk,
		      reset => reset,
		      BREAKPOINT_NOT => BREAKPOINT_NOT
		      );

  -- The reset signal
  process(clk)
  begin
    if (clk'event and clk = '1') then
      reset <= '0';
    end if;
  end process;

end simulate;
------------------------------------------------------------------------------