-- A demonstration of copying from one memory section to another
-- In simulation it will run until you quit.  In execution, it will
-- terminate by raising BREAKPOINT_NOT when all F's are encountered
-- in the copy.
-- Brent Nelson  12/12/95

-- Include all the important stuff
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library TERAMAC;
use TERAMAC.memdecl.all;

---------------------
-- User's main entity
---------------------
entity memcpy is
    port(
	 clk : in std_ulogic;
	 reset : in std_ulogic;
	 BREAKPOINT_NOT : out std_ulogic
	 );
end;

--------------------
-- Main architecture
--------------------
architecture archBody of memcpy is

  -- Constants
  constant DW : integer := 32;
  constant AW : integer := 21;
  constant BW : integer := 4;

  -- Signals for the memory
  signal Data_Out 	: std_logic_vector(DW-1 downto 0);
  signal Data_In 	: std_logic_vector(DW-1 downto 0);
  signal Byte_En_L 	: std_logic_vector(BW-1 downto 0);
  signal Byte_En 	: std_logic_vector(BW-1 downto 0);
  signal Read_Addr 	: std_logic_vector(AW-1 downto 0);
  signal Write_Addr 	: std_logic_vector(AW-1 downto 0);

begin

  -- The memory
  mem: memBank
    generic map(
		dw => DW,
		aw => AW,
		bw => BW
-- pragma synthesis_off
                ,
		LoadFile => "mem.in",
		FileType => HEX
-- pragma synthesis_on
		)
    port map(
	     clk => clk,
	     Read_Data => Data_Out,
	     Read_Addr => Read_Addr,
	     Write_Data => Data_In,
	     Byte_En_L => Byte_En_L,
	     Write_Addr => Write_Addr
	     );


  Byte_En_L <= NOT(Byte_En);
  Byte_En <= (others => NOT(reset));

  process(clk)
  begin
    if (clk'event and clk = '1') then
      Data_In <= Data_Out;
    end if;
  end process;
  
  -- A counter to step through memory for addressing
  process(clk, reset)
  begin
    if (clk'event and clk = '1') then
      if (reset = '1') then
	Read_Addr <= (others => '0');
      else
	Read_Addr <= Read_Addr + 1;
      end if;
    end if;
  end process;

  -- Another counter to step through memory
  process(Read_Addr)
  begin
    Write_Addr <= Read_Addr - 1;
    Write_Addr(6) <= '1';
  end process;

  -- Break when all 1's read
  BREAKPOINT_NOT <= '0' when Data_In = "11111111111111111111111111111111"
    else '1';

end archBody;
------------------------------------------------------------------------------