library ieee;
use ieee.std_logic_1164.all;

library TERAMAC;
use TERAMAC.memdecl.all;

entity membank is 
  generic (
	   dw : integer;
	   aw : integer;
	   bw : integer
-- pragma synthesis_off
           ;
	   LoadFile : string;
	   FileType : File_Type
-- pragma synthesis_on
	   );
  port(
	 clk			: in std_ulogic;   
	 Read_Data	        : buffer std_logic_vector(dw-1 downto 0);
	 Read_Addr	        : in  std_logic_vector(aw-1 downto 0);
	 Write_Data	        : in std_logic_vector(dw-1 downto 0);
	 Byte_En_L		: in std_logic_vector(bw-1 downto 0);
	 Write_Addr	        : in  std_logic_vector(aw-1 downto 0)
	 );
end membank;

architecture logic of membank is

begin
  -- pragma synthesis_off
  U0: sim_membank
    generic map(
		Load_File => LoadFile,
		Size => 2**aw,
		Mem_File_Type => FileType
		)
    port map(
	     clk => clk,
	     Read_Data => Read_Data,
	     Read_Addr => Read_Addr,
	     Write_Data => Write_Data,
	     Byte_En_L => Byte_En_L,
	     Write_Addr => Write_Addr
	     );
  -- pragma synthesis_on
  
end;