SPLASH2 Design Flow Overview

Step 1 - Create Your Design in VHDL

Design entry for SPLASH is done by writing VHDL code. In theory, any VHDL design and simulation system could be used for this purpose. In practice, however, Synopsys is the only option available since it is Synopsys that will be used in Step 3 to synthesize your design.

You will create a VHDL description for each XILINX chip in the SPLASH machine. If you desire, you may design a single XILINX chip and have all SPLASH processing elements (PE's) use that design. Conversely, you may design n different chips with different PE's executing different functions.

The design of a SPLASH PE is not done in a vacuum - a complete template giving input and output ports should be used as a starting point for any design. In addition, existing SPLASH VHDL libraries of data type declarations and useful functions should be used to ensure that your design will work when downloaded to SPLASH.

Step 2 - Simulate Your Design Using Synopsys' VHDLDBX

A complete simulation environment for SPLASH exists as compiled VHDL entities and architectures. When you simulate your design using the Synopsys tools you will see a complete SPLASH system being simulated including the XL and XR interface chips and FIFOs, the individual PE's and their associated memories, the crossbar, etc. Thus, in theory if the design operates correctly in the simulation it should operate correctly when downloaded.

The simulation environment provides a number of helpful features to assist you in debugging your design such as:

File input/output - the XL processor in SPLASH can take input for the array from a text file and the XR processor can write computed outputs to a text file.
Memory access errors - the VHDL model for the individual PE memories will flag accesses to uninitialized memory locations, etc.
Memory loading - the environment will allow you to specify initial memory contents if desired.

This step of the design flow is done on an HP 700 machine where the Synopsys tools have been installed.

Step 3 - Synthesize Your Design to an XNF File

Once you are happy with the functionality of your design you will use the Synopsys tools to synthesize the VHDL into a XILINX XNF file. This step can be relatively trivial in that a script called vhdl2xnf is used to do the conversion. In the synthesis step your VHDL code is compiled and mapped onto the specific XILINX parts that exist in SPLASH. This mapping is done right down to the I/O pin locations to ensure that the finished chip will work when downloaded into SPLASH.

It is in this step that you provide the compilation constraints (such as operating speed requirements) that ensure that your design will operate according to specification. Once you have completed this step you may view the resulting synthesized gate-level logic using design_analyzer from Synopsys. This step of the design flow is done on an HP 700 machine where the Synopsys tools have been installed.

Step 4 - Convert Your XNF File to a BIT File

This step involves executing the xnf2bit script which physically maps the synthesized logic onto the XILINX part. The result is a BIT file which may be downloaded into the SPLASH XILINX parts. In addition, more detailed timing characteristics of the XILINX parts are available at the conclusion of this step. This step of the design flow is done on an HP 700 machine where the Synopsys tools have been installed.

Step 5 - Execute Your Design on SPLASH2

At this point you must move the files generated in the above steps to splash - the Sun SPARC-2 front end machine.

You then may use the t2 program to download the BIT files to SPLASH, set up the input and output files, initialize the PE memories, and then repeatedly clock SPLASH. The t2 program will also let you watch signals from the SPLASH PE's. It does this by completely downloading the flip flop values from each PE between clock cycles, extracting the desired bit values and displaying them. This is done via the JTAG scan logic built into the XILINX parts. I believe one can also set values as well using t2 but I don't know how to do it.

Last updated: 27 November 1994
Brent Nelson

nelson@ee.byu.edu