The first step is to make the design. The GigaOps company has invented a C-like language for making designs. Sometimes they call it XC and sometimes DC. I didn't take the time to learn it thoroughly, but if you would like to, it is documented in the big binder. This tutorial uses ViewLogic to make the design (if you are unfamiliar with ViewLogic, you might want to see a tutorial or the ECEn 325 labs). I recommend using ViewLogic from the Spices or Counties, although it can be run from the PC which hold the GigaOps board. If you use it on the workstations it does mean you will have to change computers mid-project, but that's the way it goes. VHDL could be used also. Any method that ends up with a bitstream is fine. There is a summary of important things to know regardless of the development platform. These are the steps covered in this part of the tutorial.
Begin by creating a new project for this tutorial from Powerview.
I'll call it ~/tutorial.
Now, to make this really easy for you, I have provided all the
files you need for the tutorial. You just need to download them
to the appropriate directories. These directories are located
in your project directory.
Download the following file to your project directory (~/tutorial).
hif_444.xnf
Download the following files to your sch
directory (~/tutorial/sch).
pass.1
video_bus.1
video_data_out.1
Download the following files to your sym
directory (~/tutorial/sym).
hif_444.1
video_bus.1
video_data_out.1
Download the following files to your wir
directory (~/tutorial/wir).
pass.1
video_bus.1
video_data_out.1
Open each file in ViewLogic as I explain it. First, open the schematic
for pass. Zoom
on the host interface section. The hif_444 symbol that
you see is the interface to a macro provided by GigaOps. The macro is in the form
of a .xnf file
which is called hif_444.xnf .
That is the file you downloaded into your project directory.
To be able to use a . xnf
file as a macro, a symbol must be created like the one you are
looking at for hif_444 .
The . xnf file
must be in the project directory. The symbol must be changed to
type module and an attribute must be added to the symbol that identifies the . xnf
file. Open the hif_444
symbol if you want to see how this works. You can read more about using
.xnf macros in ViewLogic designs in the ViewLogic reference book.
The hif_444 macro interfaces
with the HBUS which is the host-to-fpga bus. It provides interactive communication
between the host and the FPGA at runtime. By the way, the host
is a PC. It provides the user interaction which for this tutorial means choosing
the different modes to display the video. The modes are normal or inverted color, and normal
or inverted luminance. The HBUS runs on the HBUS clock which comes
onto the FPGA via pin 57. The HBUS clock runs at half of the speed
of the VESA bus, which is half of 33 MHz or 16.5 MHz. There is
also a clock available that runs at the speed of the VESA bus.
For more information on different clocks and their pins, see
the big binder or the summary.
As you can see, this design uses few of the hif_444
capabilities. If you would like to know more about the hif_444,
consult the GigaOps tutorial on page 3-7. The feature we are using
here is the ability to pass a value from the host PC to the FPGA
at runtime. The way this works is, when the host sends a value,
say reg0, the host_wr_reg0 signal goes
high for one clock period. During this same clock
period, host_wr_data
carries the data that is being passed to the FPGA. We use host_wr_reg0
to enable the clock on the reg0
flip-flop which causes it to store the data. If the host had been
sending data for reg1,
the host_wr_reg1 signal would have gone high which
would have caused the reg1
flip-flop to store the data.
Now look at the video manipulation section. The video clock comes
in on pin 4. It runs at 12.2727 MHz (see the clock section in the
summary for more info on clocks). The video
information comes from the video bus macro. The
video bus macro is one that I made (not very complicated)
that does about the same thing as one that GigaOps provides. I
made it so that designs that use it can be simulated. The GigaOps
macro that does about the same thing is called vif_y0.xnf.
It would be nice to have a schematic for hif_444
also so that it could be simulated. If anyone would like to make
one, that would be great.
The only information we use from the video bus macro is the video
data. If you would like to know what the other signals are for,
see the video bus explanation.
The rest of the video manipulation section handles inverting or
passing the video data. The upper 8 bits of the video data contain
the color, or chroma, information while the lower 8 bits contain
the luminance information. The video data is split into these
two components and each one is passed on, or inverted and then
passed on. The host controls whether the data is inverted or not
via reg0 and reg1.
The video data out block simply contains the output pads and buffers
for the video data. To see the pin numbers for the video data
going off chip, open the video
data out schematic.
The control lines section enables necessary buses and disables
the memory that is on the GigaOps board. The memory control lines
are all active-low and the bus enable lines are active-high.
The last thing to notice on this schematic is the part number
at the top. This is the particular FPGA that is on the board.
Somewhere in the process you have to tell the tools which FPGA
you are using. I find it easiest just to specify it once on the
schematic and then I don't have to worry about it again. It is
specified by adding an attribute to the schematic without anything
selected. PART
is the name of the attribute and 4010PQ208-5
is the value.
Be sure to use design elements from the xc4000
library.
That concludes the logic design
Reconfigurable Logic Home Page,
ECEn Home Page
Richard D. Ross rossr@fpga.ee.byu.edu