Designing with Clay


Welcome to the Clay Design tutorial. Before completing this tutorial, you should have completed the Clay Setup Tutorial This page will guide you through the steps necessary to design with Clay, use the interactive place and route tools and use the automated CLAytools. The tutorial will cover the following major topics: NOTE: This tutorial is under construction. Please provide feedback to improve its usefullness.

Copy Tutorial Files

Before proceeding with this tutorial, copy the schematics and symbols needed for the tutorial into your cli project directory (Note: this assumes you have already created a project directory called ~/cli): cp ~wirthlim/tutorials/cli/sym/* ~/cli/sym/* cp ~wirthlim/tutorials/cli/sch/* ~/cli/sch/*

Design Entry: Counter

Before proceeding with the counter tutorial, the design.cfg file located in the counter directory must be modified. Each Clay design must be specified as either a DESIGN or COMPONENT. The netlist generator must know the design type in order to generate a correct netlist. The counter example must be specified as a COMPONENT in the design.cfg file. Modify the [BuildDataBase] section of the file design.cfg in the counter directory to specify DesignType=Component as follows: [BuildDataBase] ViewLogicLevel=CLiMacro CliPrim ; Accepts multiple items, separated by spaces TieOpenClocksTo=Global ; select global or open TieOpenResetsTo=One ; select one, global, or open DesignType=Component ; select one, Design or Component The first design excersize will involve building a counter in Viewlogic with the Clay libraries. Enter ViewDraw and open a new design called counter. From the ADD->Comp menu, add the byusheet symbol and center it on your design. byusheet.1 will be located in your primary project directory (copied with the tutorial project files).

Zoom into the lower-left hand corner of the design and enter the appropriate information into the information box.

To add Clay components to your design, access the ADD->Comp menu and select the (climacro) library in the bottom half of the window. The top half of the window contains a list of all available Clay macros for use in your design. Scroll through the list to become familiar with the symbols available to you. A text list of all Clay macros with their functional description is located here. The (cliprim) library listed underneath the (climacro) library is used for netlist conversion routines and should not be used for Clay designs.

Select the component fdmux.1 and place it on your schematic sheet. Add the components inv.1 and mux.1 to your schematic and interconnect the components as seen here. Add the following labels to the nets: Q0, CLK, R, SELA, SELB and D0 as seen here. It is also important to label each of the components on the schematic to help with the manual placement phases of design. Label the inverter inv0, the mux mux0, and the flip-flop ff0 as seen here. The low-order bit of the counter is now complete.

The counter operates according to the control signals sela and selb as follows:

sela selb Function ---- ---- -------- 0 0 Load new start value of counter 0 1 Increment counter 1 X Retain value of counter (no change)

For the second counter bit, add the components fdmux.1, inv.1, mux.1, and xond.1 to the schematic. Interconnect and label them as seen here. Create bits three and four of the counter as seen here. The counter is now complete complete and ready for simulation. Make sure the design is saved and checked.

Design Verification: Functional Simulation

To simulate the counter design, generate a simulation netlist by executing the command vsm from the Powerview command window. With a simulation netlist, enter ViewSim from the Powerview command window (if your schematic window was left open, the values of simulation will show up on the nets in the design).

Enter the following ViewSim commands to start the simulation:

restart |insure initial state of simulation clock clk 0 1 |setup the clock in the circuit l r |hold reset low h sela |hold sela high h selb |hold sela low vector d d[3:0] |set up a vector for the input bus d vector q q[3:0] |set up a vector for the output bus q assign d 0000 |initial values of input vector d watch q tc |watch vector q and signal tc sim 300 |simulate for 30 ns (reset circuit) h r |set reset back to high (circuit now stable) The environment is now ready for simulation of the counter circuit. Enter the command cycle to simulate a single clock cycle with sela=1 and selb=1. The simulator reports the following output: time = 230.0ns Q=0\H TC=0 Simulation stopped at 230.0ns. Q, the counter output, is still 0h at the end of the first clock cycle. This is correct - the control signals indicate a non-update cycle. Now, change the control signal, sela, to the value 0 and cycle the counter. l sela cycle The simulator should report the following result: time = 430.0ns Q=1\H TC=0 Simulation stopped at 430.0ns. The counter counted correctly! To verify the operation of the counter, cycle the counter 16 times. The following correct output should appear: SIM>cycle 16 time = 630.0ns Q=2\H TC=0 time = 830.0ns Q=3\H TC=0 time = 1030.0ns Q=4\H TC=0 time = 1230.0ns Q=5\H TC=0 time = 1430.0ns Q=6\H TC=0 time = 1630.0ns Q=7\H TC=0 time = 1830.0ns Q=8\H TC=0 time = 2030.0ns Q=9\H TC=0 time = 2230.0ns Q=A\H TC=0 time = 2430.0ns Q=B\H TC=0 time = 2630.0ns Q=C\H TC=0 time = 2830.0ns Q=D\H TC=0 time = 3030.0ns Q=E\H TC=0 time = 3230.0ns Q=F\H TC=1 time = 3430.0ns Q=0\H TC=0 time = 3630.0ns Q=1\H TC=0 Simulation stopped at 3630.0ns. Now, see if the counter can properly load in parallel by setting the control signal selb: SIM>l selb SIM>assign d 1010 SIM>cycle time = 3830.0ns Q=A\H TC=0 Simulation stopped at 3830.0ns. The counter successfully loaded the value 1010.

Releasing the parallel load and cycling will increment the counter.

SIM>h selb SIM>cycle 4 time = 4030.0ns Q=B\H TC=0 time = 4230.0ns Q=C\H TC=0 time = 4430.0ns Q=D\H TC=0 time = 4630.0ns Q=E\H TC=0 Simulation stopped at 4630.0ns. The counter appears to operate correctly and is ready for place and route.

Manual Place and Route

Change to your cli project directory and start ct (ClayTools): cd ~/cli ct & Select the option Netlist->Viewlogic->CDB Netlist. A correct CDB netlist should be available.

Enter the Interact tool by selecting the option Layout->Interact->Interact with Defaults (-g) from the ct design window. The interactive editor should appear. Note: Interact will sometimes behave unpredictably if other X applications steal too many colors from the display. You may have to close other applications.

Interact operates in one of three distinct modes:

To preserve the interconnection of the counter designed in Viewlogic, this tutorial will operate only in the Netlist driven mode.

To get a greater feel of the interact tool, try some of the following commands:

Zoom Out F8 Zoom In F7 Zoom Full F10 Zoom Detail F6 At the full Zoom level, the entire 56x56 array of logic cells are visable. Move around the screen by holding down the right mouse button and moving the mouse to the various borders on the screen. This allows you to move without having to use the scroll bars.

Execute the command Design->Place Instance to obtain the place component menu. Select the first component in the menu, FF0, with the mouse and select OK menu button. Note: Do not hit the CANCEL button - a bug in interact will cause interact to crash or act unpredictably. A yellow dotted square will appear on one of the interact cells indicating the position of the component. To place the component on a different cell, point the mouse to a vacant cell and click the left mouse button. The yellow square should have moved to the new location. When you have chosen an appropriate position for the component, press the middle mouse button to secure the location of the component.

Select the component by holding down the right mouse button and dragging the mouse across the component. Selection is indicated by a solid yellow square. Move the component by selecting the Edit->Move Selection menu. Select a different location of the component by clicking the left mouse button over a vacant cell. Zoom Full with F10. You will see the FF0 component as a small dot on the full view. Zoom Detail anywhere on the FPGA.

The three colored labels on the left of the FF0 cell indicate the three inputs to the cell. The cell has three inputs: red, green and blue and one output: red. The schematic symbol inside the cell indicates that the function is a MUX followed by a flip-flop. Using the same command to place the component, FF0, place the component INV0 directly underneath FF0. Now place the component MUX0 directly to the left of INV0 as seen here. The purple lines connecting the three components is the "rats nest" that indicates the connectivity of the three modules.

Because the output of the inverter, INV0, is on the blue output, it is unable to connect to the red input of the multiplexer, MUX0. In addition, since the output of the flip-flop, FF0, is red and enters the green input of INV0, it is not routable. The design could be routed if the modules are spread apart or if the port colors change. Change the port locations of the inverter by placing the mouse over the inverter and pressing the middle mouse four times. Notice that the colored ports change with each mouse click. The rats nest indicates that the two connections are routable.

Move the mouse over the purple wire connecting the inverter to the multiplexer. A rectangular yellow box should surround the purple wire. The yellow box indicates that a route is possible. Click the middle mouse button to complete the route. Follow the same instructions to route the flip-flop to the inverter. The two nets should be routed.

The purple line in the middle of the flip-flop indicates that the output of the flip-flop is connected to one of the inputs. Connect this feedback signal by routing through the block to the right of the flip-flop. Begin routing the net from the multiplexer to the flip-flop by connecting the red output to the cell on top of the multiplexer. To complete the route from the multiplexer to the flip-flop, place the mouse over the cell above the multiplexer and click the middle mouse. This causes the cell to perform a cross-over function (red-in goes to blue-out). Now complete the route to the flip-flop on the blue line.

Build the second bit of the counter as seen here. Complete the design by placing and routing all components associated with bits three and four as seen here. The design is placed and routed. Note: This design is not an optimal implementation of a parallel loadable counter in Clay. A more optimal approach will be provided as the tutorial progresses.


Last Modified: 2 March 1995

Please send comments to:

grahamp@salt.ee.byu.edu