Library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   use IEEE.std_logic_unsigned.ALL;

-- 32-bit counter implemented on the RIPP10 board.
-- Counter counts up with each clock input or resets to zero
-- when reset input is high.

-- clk = fast1, reset = fast2, cnt = gl31..gl00

entity u5 IS 
  port(clk,reset : in BIT; cout: buffer std_logic_vector (31 DOWNTO 0);
  cnt : in std_logic_vector (31 Downto 0);
  wr,oe,rcs,a0,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13 : in std_logic;
  a14,a15,a16,a17,a18,d0,d1,d2,d3,d4,d5,d6,d7,b00     : in std_logic;
  b01,b02,b03,b04,b05,b06,b07,b08,b09,b10,b11,b12     : in std_logic;
  b13,b14,b15,y00,y01,y02,y03,y04,y05,y06,y07,y08     : in std_logic;
  y09,y10,y11,y12,y13,y14,y15,y16,y17,y18,y19,y20     : in std_logic;
  y21,y22,y23,y24,y25,y26,y27,y28,y29,y30,y31         : in std_logic;
  r00,r01,r02,r03,r04                                 : in std_logic;
  r05,r06,r07,r08,r09,r10,r11,r12,r13,r14,r15,r16     : in std_logic;
  r17,r18,r19,r20,r21,r22,r23,r24,r25,r26,r27,r28     : in std_logic;
  r29,r30,r31,gl32,gl33,gl34,gl35                     : in std_logic;
  fast0,fast3,rdy,cs                                  : in std_logic );
end u5;


architecture u5_arch of u5 is
begin
  
  cout(31 downto 0) <= cnt(31 downto 0);

end u5_arch;