Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.ALL; -- 32-bit counter implemented on the RIPP10 board. -- Counter counts up with each clock input or resets to zero -- when reset input is high. -- This counter also writes its output on every clock cycle to the memory -- clk = fast1, reset = fast2, cnt = gl31..gl00 -- add = a(16..0), data = d(7..0) entity testmem IS port(clk,reset : in BIT; cnt: buffer std_logic_vector (31 DOWNTO 0); add : out std_logic_vector (16 downto 0); data: out std_logic_vector (7 downto 0); a17 : out std_logic; wr,oe,rcs : out std_logic; a18,b00 : in std_logic; b01,b02,b03,b04,b05,b06,b07,b08,b09,b10,b11,b12 : in std_logic; b13,b14,b15,y00,y01,y02,y03,y04,y05,y06,y07,y08 : in std_logic; y09,y10,y11,y12,y13,y14,y15,y16,y17,y18,y19,y20 : in std_logic; y21,y22,y23,y24,y25,y26,y27,y28,y29,y30,y31,gr00 : in std_logic; gr01,gr02,gr03,gr04,gr05,gr06,gr07,gr08,gr09,gr10 : in std_logic; gr11,gr12,gr13,gr14,gr15,gr16,gr17,gr18,gr19,gr20 : in std_logic; gr21,gr22,gr23,gr24,gr25,gr26,gr27,gr28,gr29,gr30 : in std_logic; gr31,r00,r01,r02,r03,r04 : in std_logic; r05,r06,r07,r08,r09,r10,r11,r12,r13,r14,r15,r16 : in std_logic; r17,r18,r19,r20,r21,r22,r23,r24,r25,r26,r27,r28 : in std_logic; r29,r30,r31,gl32,gl33,gl34,gl35 : in std_logic; fast0,fast3,rdy,cs : in std_logic ); end testmem; architecture testmem_arch of testmem is begin rcs <= '0'; oe <= '1'; a17 <= '1'; add(16 downto 0) <= cnt(16 downto 0); data(7 downto 0) <= cnt(7 downto 0); mem:process(clk) begin if (clk = '0') then wr <= '0'; end if; end process mem; CP:process (reset,clk,cnt) begin if (clk'event and clk='1') then if reset = '1' then cnt <= "00000000000000000000000000000000"; else cnt <= cnt + 1; end if; end if; end process CP; end testmem_arch;