CHIP testmem BEGIN DEVICE = EPF81188GC232-3; "|wr" : OUTPUT_PIN = T5; "|oe" : OUTPUT_PIN = T10; "|rcs" : OUTPUT_PIN = T12; "|add_0_" : OUTPUT_PIN = U13; "|add_1_" : OUTPUT_PIN = U12; "|add_2_" : OUTPUT_PIN = U11; "|add_3_" : OUTPUT_PIN = U10; "|add_4_" : OUTPUT_PIN = U9; "|add_5_" : OUTPUT_PIN = U8; "|add_6_" : OUTPUT_PIN = U7; "|add_7_" : OUTPUT_PIN = U6; "|add_8_" : OUTPUT_PIN = T7; "|add_9_" : OUTPUT_PIN = T8; "|add_10_" : OUTPUT_PIN = T11; "|add_11_" : OUTPUT_PIN = T9; "|add_12_" : OUTPUT_PIN = U5; "|add_13_" : OUTPUT_PIN = T6; "|add_14_" : OUTPUT_PIN = U4; "|add_15_" : OUTPUT_PIN = T3; "|add_16_" : OUTPUT_PIN = U3; "|a17" : OUTPUT_PIN = T4; "|a18" : INPUT_PIN = U2; "|data_0_" : OUTPUT_PIN = U14; "|data_1_" : OUTPUT_PIN = U15; "|data_2_" : OUTPUT_PIN = U16; "|data_3_" : OUTPUT_PIN = R15; "|data_4_" : OUTPUT_PIN = T16; "|data_5_" : OUTPUT_PIN = T15; "|data_6_" : OUTPUT_PIN = T14; "|data_7_" : OUTPUT_PIN = T13; "|b00" : INPUT_PIN = T2; "|b01" : INPUT_PIN = R3; "|b02" : INPUT_PIN = P4; "|b03" : INPUT_PIN = R5; "|b04" : INPUT_PIN = P5; "|b05" : INPUT_PIN = R6; "|b06" : INPUT_PIN = R7; "|b07" : INPUT_PIN = R8; "|b08" : INPUT_PIN = R9; "|b09" : INPUT_PIN = P9; "|b10" : INPUT_PIN = R10; "|b11" : INPUT_PIN = R11; "|b12" : INPUT_PIN = R12; "|b13" : INPUT_PIN = R13; "|b14" : INPUT_PIN = P13; "|b15" : INPUT_PIN = P14; "|y00" : INPUT_PIN = B2; "|y01" : INPUT_PIN = B3; "|y02" : INPUT_PIN = a4; "|y03" : INPUT_PIN = B4; "|y04" : INPUT_PIN = d4; "|y05" : INPUT_PIN = a5; "|y06" : INPUT_PIN = C5; "|y07" : INPUT_PIN = d5; "|y08" : INPUT_PIN = a6; "|y09" : INPUT_PIN = B6; "|y10" : INPUT_PIN = C6; "|y11" : INPUT_PIN = a8; "|y12" : INPUT_PIN = B8; "|y13" : INPUT_PIN = C8; "|y14" : INPUT_PIN = a9; "|y15" : INPUT_PIN = B9; "|y16" : INPUT_PIN = C9; "|y17" : INPUT_PIN = D9; "|y18" : INPUT_PIN = a10; "|y19" : INPUT_PIN = B10; "|y20" : INPUT_PIN = C10; "|y21" : INPUT_PIN = a12; "|y22" : INPUT_PIN = B12; "|y23" : INPUT_PIN = C12; "|y24" : INPUT_PIN = a13; "|y25" : INPUT_PIN = C13; "|y26" : INPUT_PIN = D13; "|y27" : INPUT_PIN = a14; "|y28" : INPUT_PIN = B14; "|y29" : INPUT_PIN = D14; "|y30" : INPUT_PIN = B15; "|y31" : INPUT_PIN = B16; "|gr00" : INPUT_PIN = B17; "|gr01" : INPUT_PIN = C16; "|gr02" : INPUT_PIN = C15; "|gr03" : INPUT_PIN = D17; "|gr04" : INPUT_PIN = D16; "|gr05" : INPUT_PIN = D15; "|gr06" : INPUT_PIN = E17; "|gr07" : INPUT_PIN = F17; "|gr08" : INPUT_PIN = F16; "|gr09" : INPUT_PIN = F15; "|gr10" : INPUT_PIN = G17; "|gr11" : INPUT_PIN = G16; "|gr12" : INPUT_PIN = H17; "|gr13" : INPUT_PIN = H15; "|gr14" : INPUT_PIN = J17; "|gr15" : INPUT_PIN = J16; "|gr16" : INPUT_PIN = J15; "|gr17" : INPUT_PIN = J14; "|gr18" : INPUT_PIN = K17; "|gr19" : INPUT_PIN = K15; "|gr20" : INPUT_PIN = L17; "|gr21" : INPUT_PIN = L16; "|gr22" : INPUT_PIN = M17; "|gr23" : INPUT_PIN = M16; "|gr24" : INPUT_PIN = M15; "|gr25" : INPUT_PIN = M14; "|gr26" : INPUT_PIN = N16; "|gr27" : INPUT_PIN = N15; "|gr28" : INPUT_PIN = P16; "|gr29" : INPUT_PIN = P15; "|gr30" : INPUT_PIN = R16; "|gr31" : INPUT_PIN = T17; "|r00" : INPUT_PIN = B1; "|r01" : INPUT_PIN = C2; "|r02" : INPUT_PIN = C3; "|r03" : INPUT_PIN = d1; "|r04" : INPUT_PIN = d2; "|r05" : INPUT_PIN = d3; "|r06" : INPUT_PIN = E1; "|r07" : INPUT_PIN = F1; "|r08" : INPUT_PIN = F2; "|r09" : INPUT_PIN = F3; "|r10" : INPUT_PIN = G1; "|r11" : INPUT_PIN = G2; "|r12" : INPUT_PIN = H1; "|r13" : INPUT_PIN = H3; "|r14" : INPUT_PIN = J1; "|r15" : INPUT_PIN = J2; "|r16" : INPUT_PIN = J3; "|r17" : INPUT_PIN = J4; "|r18" : INPUT_PIN = K1; "|r19" : INPUT_PIN = K3; "|r20" : INPUT_PIN = L1; "|r21" : INPUT_PIN = L2; "|r22" : INPUT_PIN = M1; "|r23" : INPUT_PIN = M2; "|r24" : INPUT_PIN = M3; "|r25" : INPUT_PIN = M4; "|r26" : INPUT_PIN = N2; "|r27" : INPUT_PIN = N3; "|r28" : INPUT_PIN = P2; "|r29" : INPUT_PIN = P3; "|r30" : INPUT_PIN = R2; "|r31" : INPUT_PIN = T1; "|cnt_0_" : OUTPUT_PIN = P1; "|cnt_1_" : OUTPUT_PIN = N1; "|cnt_2_" : OUTPUT_PIN = H2; "|cnt_3_" : OUTPUT_PIN = E2; "|cnt_4_" : OUTPUT_PIN = a2; "|cnt_5_" : OUTPUT_PIN = a3; "|cnt_6_" : OUTPUT_PIN = B5; "|cnt_7_" : OUTPUT_PIN = d7; "|cnt_8_" : OUTPUT_PIN = C7; "|cnt_9_" : OUTPUT_PIN = B7; "|cnt_10_" : OUTPUT_PIN = D8; "|cnt_11_" : OUTPUT_PIN = a7; "|cnt_12_" : OUTPUT_PIN = D10; "|cnt_13_" : OUTPUT_PIN = D11; "|cnt_14_" : OUTPUT_PIN = C11; "|cnt_15_" : OUTPUT_PIN = B11; "|cnt_16_" : OUTPUT_PIN = a11; "|cnt_17_" : OUTPUT_PIN = D12; "|cnt_18_" : OUTPUT_PIN = B13; "|cnt_19_" : OUTPUT_PIN = a15; "|cnt_20_" : OUTPUT_PIN = a16; "|cnt_21_" : OUTPUT_PIN = a17; "|cnt_22_" : OUTPUT_PIN = E15; "|cnt_23_" : OUTPUT_PIN = E16; "|cnt_24_" : OUTPUT_PIN = F14; "|cnt_25_" : OUTPUT_PIN = H16; "|cnt_26_" : OUTPUT_PIN = K16; "|cnt_27_" : OUTPUT_PIN = N17; "|cnt_28_" : OUTPUT_PIN = P17; "|cnt_29_" : OUTPUT_PIN = U17; "|cnt_30_" : OUTPUT_PIN = P11; "|cnt_31_" : OUTPUT_PIN = P10; "|gl32" : INPUT_PIN = P8; "|gl33" : INPUT_PIN = P7; "|gl34" : INPUT_PIN = P6; "|gl35" : INPUT_PIN = F4; "|fast0" : INPUT_PIN = C1; "|clk" : INPUT_PIN = C17; "|reset" : INPUT_PIN = R1; "|fast3" : INPUT_PIN = R17; "|cs" : INPUT_PIN = E3; "|rdy" : INPUT_PIN = K2; END; DEFAULT_DEVICES BEGIN AUTO_DEVICE = "EPF8282LC84"; AUTO_DEVICE = "EPF8282TC100"; AUTO_DEVICE = "EPF8282ALC84"; AUTO_DEVICE = "EPF8282ATC100"; AUTO_DEVICE = "EPF8282VLC84"; AUTO_DEVICE = "EPF8282VTC100"; AUTO_DEVICE = "EPF8452LC84"; AUTO_DEVICE = "EPF8452GC160"; AUTO_DEVICE = "EPF8452QC160"; AUTO_DEVICE = "EPF8452ALC84"; AUTO_DEVICE = "EPF8452AGC160"; AUTO_DEVICE = "EPF8452AQC160"; AUTO_DEVICE = "EPF8636ALC84"; AUTO_DEVICE = "EPF8636AQC160"; AUTO_DEVICE = "EPF8636AGC192"; AUTO_DEVICE = "EPF8636ARC208"; AUTO_DEVICE = "EPF8820GC192"; AUTO_DEVICE = "EPF8820RC208"; AUTO_DEVICE = "EPF8820BC225"; AUTO_DEVICE = "EPF8820AQC160"; AUTO_DEVICE = "EPF8820AGC192"; AUTO_DEVICE = "EPF8820ARC208"; AUTO_DEVICE = "EPF8820ABC225"; AUTO_DEVICE = "EPF81188GC232"; AUTO_DEVICE = "EPF81188RC240"; AUTO_DEVICE = "EPF81188UC225"; AUTO_DEVICE = "EPF81188AQC208"; AUTO_DEVICE = "EPF81188AGC232"; AUTO_DEVICE = "EPF81188ARC240"; AUTO_DEVICE = "EPF81500GC280"; AUTO_DEVICE = "EPF81500RC304"; ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; END; LOGIC_OPTIONS BEGIN END; TIMING_POINT BEGIN TPD = null; TCO = null; TSU = null; FREQUENCY = null; CUT_ALL_BIDIR = ON; CUT_ALL_CLEAR_PRESET = ON; END; PROBES BEGIN END; GLOBAL_PROJECT_DEVICE_OPTIONS BEGIN RESERVED_LCELLS_PERCENT = 0; RESERVED_PINS_PERCENT = 0; SECURITY_BIT = OFF; FLEX8000_USER_CLOCK = OFF; FLEX8000_AUTO_RESTART = OFF; FLEX8000_RELEASE_CLEARS = OFF; FLEX8000_ENABLE_DCLK_OUTPUT = OFF; FLEX8000_DISABLE_TIME_OUT = ON; FLEX8000_CONFIG_SCHEME = PASSIVE_PARALLEL_ASYNCHRONOUS; FLEX8000_ENABLE_JTAG = OFF; FLEX8000_DATA0 = UNRESERVED; FLEX8000_DATA1_TO_DATA7 = UNRESERVED; FLEX8000_nWS_nRS_nCS_CS = UNRESERVED; FLEX8000_RDYnBUSY = UNRESERVED; FLEX8000_RDCLK = UNRESERVED; FLEX8000_SDOUT = UNRESERVED; FLEX8000_ADD0_TO_ADD12 = UNRESERVED; FLEX8000_ADD13 = UNRESERVED; FLEX8000_ADD14 = UNRESERVED; FLEX8000_ADD15 = UNRESERVED; FLEX8000_ADD16 = UNRESERVED; FLEX8000_ADD17 = UNRESERVED; FLEX8000_CLKUSR = UNRESERVED; END; GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS BEGIN MULTI_LEVEL_SYNTHESIS = OFF; AUTO_GLOBAL_CLOCK = ON; AUTO_GLOBAL_CLEAR = OFF; AUTO_GLOBAL_PRESET = OFF; AUTO_GLOBAL_OE = OFF; AUTO_IO_CELL_REGISTERS = OFF; STYLE = NORMAL; DEVICE_FAMILY = FLEX8000; IGNORE_CLIQUE_ASSIGNMENTS = OFF; IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; IGNORE_TIMING_ASSIGNMENTS = OFF; IGNORE_CHIP_ASSIGNMENTS = OFF; IGNORE_PIN_ASSIGNMENTS = OFF; IGNORE_LC_ASSIGNMENTS = OFF; IGNORE_DEVICE_ASSIGNMENTS = OFF; AUTO_REGISTER_PACKING = OFF; END; COMPILER_PROCESSING_CONFIGURATION BEGIN DESIGN_DOCTOR = "OFF"; DESIGN_DOCTOR_RULES = "EPLD"; FUNCTIONAL_SNF_EXTRACTOR = "OFF"; OPTIMIZE_TIMING_SNF = "OFF"; LINKED_SNF_EXTRACTOR = "OFF"; RPT_FILE_EQUATIONS = "ON"; RPT_FILE_HIERARCHY = "ON"; RPT_FILE_LCELL_INTERCONNECT = "ON"; RPT_FILE_USER_ASSIGNMENTS = "ON"; GENERATE_JEDEC_FILE = "OFF"; GENERATE_AHDL_TDO_FILE = "OFF"; SMART_RECOMPILE = "OFF"; TIMING_SNF_EXTRACTOR = "ON"; FITTER_SETTINGS = "NORMAL"; END; COMPILER_INTERFACES_CONFIGURATION BEGIN EDIF_NETLIST_WRITER = "OFF"; EDIF_OUTPUT_VERSION = "200"; XNF_EMULATE_TRI_STATE_BUSES = "INTERNAL_LOGIC"; XNF_TRANSLATE_INTERNAL_NODE_NAMES = "ON"; XNF_GENERATE_AHDL_TDX_FILE = "ON"; VERILOG_NETLIST_WRITER = "OFF"; VHDL_NETLIST_WRITER = "OFF"; EDIF_INPUT_LMF1 = "altsyn.lmf"; EDIF_INPUT_LMF2 = "/fpga2/users/petersr/dsphardware/synopsys/*.lmf"; EDIF_OUTPUT_EDC_FILE = "vwl.edc"; EDIF_INPUT_VCC = "VDD"; EDIF_INPUT_GND = "GND"; EDIF_OUTPUT_VCC = "VCC"; EDIF_OUTPUT_GND = "ground"; EDIF_INPUT_USE_LMF1 = "ON"; EDIF_INPUT_USE_LMF2 = "OFF"; EDIF_OUTPUT_USE_EDC = "OFF"; EDIF_OUTPUT_DELAY_CONSTRUCTS = "ON"; EDIF_OUTPUT_MAP_ILLEGAL_CHAR = "ON"; EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = "ON"; EDIF_OUTPUT_FORCE_0NS_DELAYS = "OFF"; EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = "ON"; END; CUSTOM_DESIGN_DOCTOR_RULES BEGIN RIPPLE_CLOCKS = ON; GATED_CLOCKS = ON; MULTI_LEVEL_CLOCKS = ON; MULTI_CLOCK_NETWORKS = ON; STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; PRESET_CLEAR_NETWORKS = ON; ASYNCHRONOUS_INPUTS = ON; DELAY_CHAINS = ON; RACE_CONDITIONS = ON; EXPANDER_NETWORKS = ON; MASTER_RESET = OFF; END; SIMULATOR_CONFIGURATION BEGIN USE_DEVICE = OFF; SETUP_HOLD = OFF; CHECK_OUTPUTS = OFF; OSCILLATION = OFF; OSCILLATION_TIME = 0.0ns; GLITCH = OFF; GLITCH_TIME = 0.0ns; SIMULATION_INPUT_FILE = null; START_TIME = 0.0ns; END_TIME = 0.0ns; END; TIMING_ANALYZER_CONFIGURATION BEGIN END; PROGRAMMER_CONFIGURATION BEGIN END; OTHER_CONFIGURATION BEGIN ORIGINAL_MAXPLUS2_VERSION = "5.2"; DEFAULT_9K_EXP_PER_LCELL = "1/2"; EXPLICIT_FAMILY = "0"; COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; NORMAL_LCELL_INSERT = "ON"; CARRY_OUT_PINS_LCELL_INSERT = "ON"; ROW_PINS_LCELL_INSERT = "ON"; LCELLS_PER_ROW_PERCENT = "100"; EXP_PER_LCELL_PERCENT = "100"; FAN_IN_PER_LCELL_PERCENT = "100"; ROW_PINS_PERCENT = "50"; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = 32; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = ON; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 BEGIN CASCADE_CHAIN = AUTO; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = AUTO; CARRY_CHAIN_LENGTH = 32; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 BEGIN CASCADE_CHAIN = MANUAL; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = MANUAL; CARRY_CHAIN_LENGTH = 32; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; REGISTER_OPTIMIZATION = OFF; END;