-- MAX+plus II Version 5.0 8/5/94 -- Modified: 11/07/94 20:52:44 -- Configuration for 8452 used to load the 81188 FPGAs with -- configuration data. %---------------------------------------------------------------------------- ----------------------------------------------------------------------------% CONSTANT BASE_ADDRESS = B"1100000"; CONSTANT RESET_ADDRESS = H"00"; CONSTANT WS_ADDRESS = H"01"; CONSTANT CS_ADDRESS = H"02"; CONSTANT STATUS_ADDRESS = H"03"; CONSTANT JTAG_ADDRESS = H"04"; SUBDESIGN ripload5 ( data[15..0] : BIDIR; addr[9..0] : INPUT; pcclk : INPUT; /aen : INPUT; /iow : INPUT; /ior : INPUT; /iordy : BIDIR; dmareq3 : BIDIR; /dmaack3 : BIDIR; dmareq7 : BIDIR; /dmaack7 : BIDIR; dmatc : BIDIR; intreq7 : BIDIR; intreq15 : BIDIR; /io16 : BIDIR; sbhe : BIDIR; global[35..00] : OUTPUT; cs[8..1] : OUTPUT; rdy[8..1] : INPUT; /array_status : INPUT; array_conf_done : BIDIR; /array_config : OUTPUT; /bank_oe[4..1] : OUTPUT; bank_out[4..1] : OUTPUT; extout[3..0] : OUTPUT; extin[2..0] : INPUT; fast[3..0] : INPUT; sclk[1..0] : OUTPUT; osc : INPUT; tclk : OUTPUT; tms : OUTPUT; rstb : OUTPUT; ) VARIABLE confdata[7..0] : DFF; % register for latching 81188 configuration data % cs_reg[8..1] : DFF; % register for individual chip selects % jtag_reg[2..0] : DFF; % register for JTAG signals % select : SOFT; % download circuit selected % write : SOFT; % selected for writing % read : SOFT; % selected for reading % read_status : SOFT; % selected and reading array status % /array_ws : SOFT; % writing data to array % /array_rs : SOFT; % reading data from array % /array_cs : SOFT; % global array chip select % BEGIN select = (addr[9..3]==BASE_ADDRESS) & !/aen; write = select & !/iow; % goes high when downloader is written to % read = select & !/ior; % goes high when downloader is read from % array_conf_done = TRI(GND,GND); % can be used to delay start-up of 81188's % % a low pulse resets all the 81188's % /array_config = !(write & addr[2..0]==RESET_ADDRESS); % a low pulse occurs when config data is written to the 81188's % global00 = TRI( /array_ws, !array_conf_done ); /array_ws = !(write & addr[2..0]==WS_ADDRESS); % read strobe should be high when 81188's are not being read % global01 = TRI( /array_rs, !array_conf_done ); /array_rs = VCC; % global 81188 chip select should be low to enable configuration % global03 = TRI( /array_cs, !array_conf_done ); /array_cs = GND; % register for holding chip select values for individual 81188's % cs_reg1 = LCELL(data0); cs_reg2 = LCELL(data1); cs_reg3 = LCELL(data2); cs_reg4 = LCELL(data3); cs_reg5 = LCELL(data4); cs_reg6 = LCELL(data5); cs_reg7 = LCELL(data6); cs_reg8 = LCELL(data7); cs_reg[8..1].clk = !(write & addr[2..0]==CS_ADDRESS); % chip selects for each 81188 % cs1 = TRI( cs_reg1, !array_conf_done ); cs2 = TRI( cs_reg2, !array_conf_done ); cs3 = TRI( cs_reg3, !array_conf_done ); cs4 = TRI( cs_reg4, !array_conf_done ); cs5 = TRI( cs_reg5, !array_conf_done ); cs6 = TRI( cs_reg6, !array_conf_done ); cs7 = TRI( cs_reg7, !array_conf_done ); cs8 = TRI( cs_reg8, !array_conf_done ); % register for latching configuration data for 81188s % confdata0 = LCELL(data0); confdata1 = LCELL(data1); confdata2 = LCELL(data2); confdata3 = LCELL(data3); confdata4 = LCELL(data4); confdata5 = LCELL(data5); confdata6 = LCELL(data6); confdata7 = LCELL(data7); confdata[7..0].clk = !/array_ws; % data bus that carries configuration data to the 81188s % global04 = TRI( LCELL(confdata0), !array_conf_done ); global05 = TRI( LCELL(LCELL(confdata1)), !array_conf_done ); global06 = TRI( LCELL(confdata2), !array_conf_done ); global07 = TRI( LCELL(confdata3), !array_conf_done ); global08 = TRI( LCELL(confdata4), !array_conf_done ); global09 = TRI( LCELL(confdata5), !array_conf_done ); global10 = TRI( LCELL(confdata6), !array_conf_done ); global11 = TRI( LCELL(confdata7), !array_conf_done ); % allows query of status and conf_done signals % data0 = TRI( LCELL(/array_status), read_status ); data1 = TRI( LCELL(array_conf_done), read_status ); read_status = LCELL(read & addr[2..0]==STATUS_ADDRESS); % JTAG signals for the IQ160s % jtag_reg0 = LCELL(data0); jtag_reg1 = LCELL(data1); jtag_reg2 = LCELL(data2); jtag_reg[2..0].clk = !(write & addr[2..0]==JTAG_ADDRESS); tclk = jtag_reg0; tms = jtag_reg1; rstb = jtag_reg2; % all the rest keeps the chip outputs from frying anything % data2 = TRI(GND, GND); data3 = TRI(GND, GND); data4 = TRI(GND, GND); data5 = TRI(GND, GND); data6 = TRI(GND, GND); data7 = TRI(GND, GND); data8 = TRI(GND, GND); data9 = TRI(GND, GND); data10 = TRI(GND, GND); data11 = TRI(GND, GND); data12 = TRI(GND, GND); data13 = TRI(GND, GND); data14 = TRI(GND, GND); data15 = TRI(GND, GND); /iordy = TRI(GND, GND); dmareq3 = TRI(GND, GND); dmareq7 = TRI(GND, GND); /dmaack3= TRI(GND, GND); /dmaack7= TRI(GND, GND); dmatc = TRI(GND, GND); intreq7 = TRI(GND, GND); intreq15= TRI(GND, GND); /io16 = TRI(GND, GND); sbhe = TRI(GND, GND); global02 = LCELL(pcclk); global12 = TRI(GND, GND); global13 = TRI(GND, GND); global14 = TRI(GND, GND); global15 = TRI(GND, GND); global16 = TRI(GND, GND); global17 = TRI(GND, GND); global18 = TRI(GND, GND); global19 = TRI(GND, GND); global20 = TRI(GND, GND); global21 = TRI(GND, GND); global22 = TRI(GND, GND); global23 = TRI(GND, GND); global24 = TRI(GND, GND); global25 = TRI(GND, GND); global26 = TRI(GND, GND); global27 = TRI(GND, GND); global28 = TRI(GND, GND); global29 = TRI(GND, GND); global30 = TRI(GND, GND); global31 = TRI(GND, GND); global32 = TRI(GND, GND); global33 = TRI(GND, GND); global34 = TRI(GND, GND); global35 = TRI(GND, GND); /bank_oe[4..1] = VCC; bank_out[4..1] = VCC; extout0 = TRI(GND,GND); extout1 = TRI(GND,GND); extout2 = TRI(GND,GND); extout3 = TRI(GND,GND); sclk0 = GND; sclk1 = GND; END;