CHIP ripload5 BEGIN DEVICE = EPF8452GC160 {tdf}; FLEX8000_DATA0 = UNRESERVED; FLEX8000_nWS_nRS_nCS_CS = UNRESERVED; FLEX8000_DATA1_TO_DATA7 = UNRESERVED; FLEX8000_RDYnBUSY = UNRESERVED; FLEX8000_RDCLK = UNRESERVED; FLEX8000_SDOUT = UNRESERVED; FLEX8000_ADD0_TO_ADD12 = UNRESERVED; FLEX8000_ADD13 = UNRESERVED; FLEX8000_ADD14 = UNRESERVED; FLEX8000_ADD15 = UNRESERVED; FLEX8000_ADD16 = UNRESERVED; FLEX8000_ADD17 = UNRESERVED; FLEX8000_USER_CLOCK = OFF; FLEX8000_ENABLE_DCLK_OUTPUT = OFF; FLEX8000_DISABLE_TIME_OUT = OFF; FLEX8000_ENABLE_JTAG = OFF; FLEX8000_CONFIG_SCHEME = PASSIVE_PARALLEL_ASYNCHRONOUS; SECURITY = OFF; TURBO_BIT = OFF; "|data0" : BIDIR_PIN = K13 {tdf}; "|data1" : BIDIR_PIN = N15 {tdf}; "|data2" : BIDIR_PIN = R14 {tdf}; "|data3" : BIDIR_PIN = P13 {tdf}; "|data4" : BIDIR_PIN = R13 {tdf}; "|data5" : BIDIR_PIN = R12 {tdf}; "|data6" : BIDIR_PIN = P10 {tdf}; "|data7" : BIDIR_PIN = P8 {tdf}; "|data8" : BIDIR_PIN = R6 {tdf}; "|data9" : BIDIR_PIN = N5 {tdf}; "|data10" : BIDIR_PIN = P5 {tdf}; "|data11" : BIDIR_PIN = R4 {tdf}; "|data12" : BIDIR_PIN = R2 {tdf}; "|data13" : BIDIR_PIN = P1 {tdf}; "|data14" : BIDIR_PIN = N3 {tdf}; "|data15" : BIDIR_PIN = N1 {tdf}; "|addr0" : INPUT_PIN = P7 {tdf}; "|addr1" : INPUT_PIN = F13 {tdf}; "|addr2" : INPUT_PIN = E15 {tdf}; "|addr3" : INPUT_PIN = D15 {tdf}; "|addr4" : INPUT_PIN = N7 {tdf}; "|addr5" : INPUT_PIN = N8 {tdf}; "|addr6" : INPUT_PIN = R9 {tdf}; "|addr7" : INPUT_PIN = P9 {tdf}; "|addr8" : INPUT_PIN = N9 {tdf}; "|addr9" : INPUT_PIN = R10 {tdf}; "|/aen" : INPUT_PIN = C6 {tdf}; "|/iow" : INPUT_PIN = N2 {tdf}; "|/ior" : INPUT_PIN = N11 {tdf}; "|/iordy" : BIDIR_PIN = P12 {tdf}; "|dmareq3" : BIDIR_PIN = R11 {tdf}; "|/dmaack3" : BIDIR_PIN = P11 {tdf}; "|dmareq7" : BIDIR_PIN = R3 {tdf}; "|/dmaack7" : BIDIR_PIN = R5 {tdf}; "|dmatc" : BIDIR_PIN = R8 {tdf}; "|intreq7" : BIDIR_PIN = N10 {tdf}; "|intreq15" : BIDIR_PIN = P6 {tdf}; "|pcclk" : INPUT_PIN = R15 {tdf}; "|sbhe" : BIDIR_PIN = R7 {tdf}; "|/io16" : BIDIR_PIN = N6 {tdf}; "|global00" : BIDIR_PIN = J1 {tdf}; "|global01" : BIDIR_PIN = H2 {tdf}; "|global02" : OUTPUT_PIN = H1 {tdf}; "|global03" : BIDIR_PIN = G2 {tdf}; "|global04" : BIDIR_PIN = G1 {tdf}; "|global05" : BIDIR_PIN = F3 {tdf}; "|global06" : BIDIR_PIN = F2 {tdf}; "|global07" : BIDIR_PIN = F1 {tdf}; "|global08" : BIDIR_PIN = E3 {tdf}; "|global09" : BIDIR_PIN = E2 {tdf}; "|global10" : BIDIR_PIN = E1 {tdf}; "|global11" : BIDIR_PIN = D2 {tdf}; "|global12" : BIDIR_PIN = D1 {tdf}; "|global13" : BIDIR_PIN = C2 {tdf}; "|global14" : BIDIR_PIN = C1 {tdf}; "|global15" : BIDIR_PIN = B1 {tdf}; "|global16" : BIDIR_PIN = B6 {tdf}; "|global17" : BIDIR_PIN = A6 {tdf}; "|global18" : BIDIR_PIN = C7 {tdf}; "|global19" : BIDIR_PIN = B7 {tdf}; "|global20" : BIDIR_PIN = A7 {tdf}; "|global21" : BIDIR_PIN = C8 {tdf}; "|global22" : BIDIR_PIN = B8 {tdf}; "|global23" : BIDIR_PIN = A8 {tdf}; "|global24" : BIDIR_PIN = C9 {tdf}; "|global25" : BIDIR_PIN = B9 {tdf}; "|global26" : BIDIR_PIN = A9 {tdf}; "|global27" : BIDIR_PIN = C10 {tdf}; "|global28" : BIDIR_PIN = B10 {tdf}; "|global29" : BIDIR_PIN = A10 {tdf}; "|global30" : BIDIR_PIN = C11 {tdf}; "|global31" : BIDIR_PIN = B11 {tdf}; "|global32" : BIDIR_PIN = A11 {tdf}; "|global33" : BIDIR_PIN = B12 {tdf}; "|global34" : BIDIR_PIN = A12 {tdf}; "|global35" : BIDIR_PIN = B13 {tdf}; "|/bank_oe1" : OUTPUT_PIN = A14 {tdf}; "|bank_out1" : OUTPUT_PIN = A13 {tdf}; "|/bank_oe2" : OUTPUT_PIN = B15 {tdf}; "|bank_out2" : OUTPUT_PIN = B14 {tdf}; "|/bank_oe3" : OUTPUT_PIN = C15 {tdf}; "|bank_out3" : OUTPUT_PIN = C14 {tdf}; "|/bank_oe4" : OUTPUT_PIN = E14 {tdf}; "|bank_out4" : OUTPUT_PIN = E13 {tdf}; "|extin0" : INPUT_PIN = G14 {tdf}; "|extin1" : INPUT_PIN = F15 {tdf}; "|extin2" : INPUT_PIN = F14 {tdf}; "|extout0" : OUTPUT_PIN = J14 {tdf}; "|extout1" : OUTPUT_PIN = H15 {tdf}; "|extout2" : OUTPUT_PIN = H14 {tdf}; "|extout3" : OUTPUT_PIN = G15 {tdf}; "|tclk" : OUTPUT_PIN = P15 {tdf}; "|tms" : OUTPUT_PIN = N14 {tdf}; "|rstb" : OUTPUT_PIN = M14 {tdf}; "|/array_status" : INPUT_PIN = L15 {tdf}; "|array_conf_done" : BIDIR_PIN = L14 {tdf}; "|/array_config" : OUTPUT_PIN = L13 {tdf}; "|cs1" : OUTPUT_PIN = B5 {tdf}; "|cs2" : OUTPUT_PIN = A4 {tdf}; "|cs3" : OUTPUT_PIN = A3 {tdf}; "|cs4" : OUTPUT_PIN = A2 {tdf}; "|cs5" : OUTPUT_PIN = M2 {tdf}; "|cs6" : OUTPUT_PIN = L3 {tdf}; "|cs7" : OUTPUT_PIN = K3 {tdf}; "|cs8" : OUTPUT_PIN = K1 {tdf}; "|rdy1" : INPUT_PIN = A5 {tdf}; "|rdy2" : INPUT_PIN = C5 {tdf}; "|rdy3" : INPUT_PIN = B4 {tdf}; "|rdy4" : INPUT_PIN = B3 {tdf}; "|rdy5" : INPUT_PIN = M1 {tdf}; "|rdy6" : INPUT_PIN = L2 {tdf}; "|rdy7" : INPUT_PIN = K2 {tdf}; "|rdy8" : INPUT_PIN = J2 {tdf}; "|fast0" : BIDIR_PIN = K15 {tdf}; "|fast1" : BIDIR_PIN = K14 {tdf}; "|fast2" : BIDIR_PIN = J15 {tdf}; "|fast3" : INPUT_PIN = D14 {tdf}; "|sclk0" : OUTPUT_PIN = P4 {tdf}; "|sclk1" : OUTPUT_PIN = P3 {tdf}; "|osc" : INPUT_PIN = C3 {tdf}; END; DEFAULT_DEVICES BEGIN AUTO_DEVICE = "EPF8282LC84"; AUTO_DEVICE = "EPF8282TC100"; AUTO_DEVICE = "EPF8282VLC84"; AUTO_DEVICE = "EPF8282VTC100"; AUTO_DEVICE = "EPF8452LC84"; AUTO_DEVICE = "EPF8452GC160"; AUTO_DEVICE = "EPF8452QC160"; AUTO_DEVICE = "EPF8452ALC84"; AUTO_DEVICE = "EPF8452AGC160"; AUTO_DEVICE = "EPF8452AQC160"; AUTO_DEVICE = "EPF8820GC192"; AUTO_DEVICE = "EPF8820RC208"; AUTO_DEVICE = "EPF8820BC225"; AUTO_DEVICE = "EPF81188GC232"; AUTO_DEVICE = "EPF81188RC240"; AUTO_DEVICE = "EPF81188UC225"; AUTO_DEVICE = "EPF81500GC280"; AUTO_DEVICE = "EPF81500RC304"; ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; END; LOGIC_OPTIONS BEGIN END; TIMING_POINT BEGIN TPD = null; TCO = null; TSU = null; FREQUENCY = null; CUT_ALL_BIDIR = ON; CUT_ALL_CLEAR_PRESET = ON; END; PROBES BEGIN END; GLOBAL_PROJECT_DEVICE_OPTIONS BEGIN RESERVED_LCELLS_PERCENT = 0 {ini}; RESERVED_PINS_PERCENT = 0 {ini}; SECURITY_BIT = 0 {ini}; FLEX8000_USER_CLOCK = OFF {ini}; FLEX8000_AUTO_RESTART = OFF {ini}; FLEX8000_RELEASE_CLEARS = OFF {ini}; FLEX8000_ENABLE_DCLK_OUTPUT = OFF {ini}; FLEX8000_DISABLE_TIME_OUT = ON {ini}; FLEX8000_CONFIG_SCHEME = PASSIVE_PARALLEL_ASYNCHRONOUS {ini}; FLEX8000_ENABLE_JTAG = OFF {ini}; FLEX8000_DATA0 = UNRESERVED {ini}; FLEX8000_DATA1_TO_DATA7 = UNRESERVED {ini}; FLEX8000_nWS_nRS_nCS_CS = UNRESERVED {ini}; FLEX8000_RDYnBUSY = UNRESERVED {ini}; FLEX8000_RDCLK = UNRESERVED {ini}; FLEX8000_SDOUT = UNRESERVED {ini}; FLEX8000_ADD0_TO_ADD12 = UNRESERVED {ini}; FLEX8000_ADD13 = UNRESERVED {ini}; FLEX8000_ADD14 = UNRESERVED {ini}; FLEX8000_ADD15 = UNRESERVED {ini}; FLEX8000_ADD16 = UNRESERVED {ini}; FLEX8000_ADD17 = UNRESERVED {ini}; FLEX8000_CLKUSR = UNRESERVED {ini}; END; GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS BEGIN PRE_VERSION_5_SYNTHESIS = ON; AUTO_GLOBAL_CLOCK = 0 {ini}; AUTO_GLOBAL_CLEAR = 0 {ini}; AUTO_GLOBAL_PRESET = 0 {ini}; AUTO_GLOBAL_OE = 0 {ini}; AUTO_IO_CELL_REGISTERS = 0 {ini}; STYLE = NORMAL {ini}; DEVICE_FAMILY = FLEX8000; IGNORE_CLIQUE_ASSIGNMENTS = OFF; IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; IGNORE_TIMING_ASSIGNMENTS = OFF; IGNORE_CHIP_ASSIGNMENTS = OFF; IGNORE_PIN_ASSIGNMENTS = OFF; IGNORE_LC_ASSIGNMENTS = OFF; IGNORE_DEVICE_ASSIGNMENTS = OFF; END; COMPILER_PROCESSING_CONFIGURATION BEGIN DESIGN_DOCTOR = ON; DESIGN_DOCTOR_RULES = FLEX; FUNCTIONAL_SNF_EXTRACTOR = 0 {ini}; OPTIMIZE_TIMING_SNF = ON; LINKED_SNF_EXTRACTOR = 0 {ini}; AUTO_LCELL_INSERTION = ON; RPT_FILE_EQUATIONS = ON {ini}; RPT_FILE_HIERARCHY = ON {ini}; RPT_FILE_LCELL_INTERCONNECT = ON {ini}; RPT_FILE_USER_ASSIGNMENTS = ON {ini}; GENERATE_JEDEC_FILE = 0 {ini}; GENERATE_AHDL_TDO_FILE = OFF; SMART_RECOMPILE = OFF; TIMING_SNF_EXTRACTOR = ON; END; COMPILER_INTERFACES_CONFIGURATION BEGIN EDIF_NETLIST_WRITER = "0" {ini}; EDIF_OUTPUT_VERSION = "200" {ini}; XNF_EMULATE_TRI_STATE_BUSES = "INTERNAL_LOGIC" {ini}; XNF_TRANSLATE_INTERNAL_NODE_NAMES = "1" {ini}; XNF_GENERATE_AHDL_TDX_FILE = "1" {ini}; VERILOG_NETLIST_WRITER = "0" {ini}; VHDL_NETLIST_WRITER = "0" {ini}; EDIF_INPUT_LMF1 = ".lmf" {ini}; EDIF_INPUT_LMF2 = ".lmf" {ini}; EDIF_OUTPUT_EDC_FILE = ".edc" {ini}; EDIF_INPUT_VCC = "VCC" {ini}; EDIF_INPUT_GND = "GND" {ini}; EDIF_OUTPUT_VCC = "VCC" {ini}; EDIF_OUTPUT_GND = "GND" {ini}; EDIF_INPUT_USE_LMF1 = "0" {ini}; EDIF_INPUT_USE_LMF2 = "0" {ini}; EDIF_OUTPUT_USE_EDC = "0" {ini}; EDIF_OUTPUT_DELAY_CONSTRUCTS = "1" {ini}; EDIF_OUTPUT_MAP_ILLEGAL_CHAR = "0" {ini}; EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = "0" {ini}; EDIF_OUTPUT_FORCE_0NS_DELAYS = "0" {ini}; EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = "0" {ini}; END; CUSTOM_DESIGN_DOCTOR_RULES BEGIN RIPPLE_CLOCKS = 1 {ini}; GATED_CLOCKS = 1 {ini}; MULTI_LEVEL_CLOCKS = 1 {ini}; MULTI_CLOCK_NETWORKS = 1 {ini}; STATIC_HAZARDS_BEFORE_SYNTHESIS = 1 {ini}; STATIC_HAZARDS_AFTER_SYNTHESIS = 0 {ini}; PRESET_CLEAR_NETWORKS = 1 {ini}; ASYNCHRONOUS_INPUTS = 1 {ini}; DELAY_CHAINS = 1 {ini}; RACE_CONDITIONS = 1 {ini}; EXPANDER_NETWORKS = 1 {ini}; MASTER_RESET = 0 {ini}; END; SIMULATOR_CONFIGURATION BEGIN USE_DEVICE = OFF; SETUP_HOLD = OFF; CHECK_OUTPUTS = OFF; OSCILLATION = OFF; OSCILLATION_TIME = 0.0ns; GLITCH = OFF; GLITCH_TIME = 0.0ns; SIMULATION_INPUT_FILE = null; START_TIME = 0.0ns; END_TIME = 0.0ns; END; TIMING_ANALYZER_CONFIGURATION BEGIN END; PROGRAMMER_CONFIGURATION BEGIN END; OTHER_CONFIGURATION BEGIN COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; ALL_STYLES = "Normal,Fast,WYSIWYG" {ini}; EXPLICIT_FAMILY = "0"; EDIT_FIT = "0" {ini}; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = 32; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = ON; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = ON; EXPANDER_FACTORING = ON; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 BEGIN CASCADE_CHAIN = AUTO; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = AUTO; CARRY_CHAIN_LENGTH = 32; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CARRY_CHAIN = IGNORE; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 BEGIN CASCADE_CHAIN = MANUAL; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = MANUAL; CARRY_CHAIN_LENGTH = 32; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; REGISTER_OPTIMIZATION = OFF; END;