%---------------------------------------------------------------------------- Interface to RIP memory tester/loader. Test memory as follows: 1. Write lower byte of 19-bit address to 0x300; 2. Write middle byte of 19-bit address to 0x301; 3. Write upper three bits of 19-bit address to 0x302; 4. Select the RAM chip to be tested by writing to 0x303 as follows: 0x01 = access RAM chip U9 through chip U1; 0x02 = access RAM chip U9 through chip U2; 0x04 = access RAM chip U10 through chip U3; 0x08 = access RAM chip U10 through chip U4; 0x10 = access RAM chip U11 through chip U5; 0x20 = access RAM chip U11 through chip U6; 0x40 = access RAM chip U12 through chip U7; 0x80 = access RAM chip U12 through chip U8; 5. Write data byte to 0x304; 6. Read data byte back from 0x304; 7. Compare written and read data. ----------------------------------------------------------------------------% CONSTANT BASE_ADDRESS = B"1100000"; DESIGN IS memintfc BEGIN DEVICE memintfc IS EPF8452GC160 BEGIN % 16-bit PC-AT data bus % data0 @ K13 : BIDIR; data1 @ N15 : BIDIR; data2 @ R14 : BIDIR; data3 @ P13 : BIDIR; data4 @ R13 : BIDIR; data5 @ R12 : BIDIR; data6 @ P10 : BIDIR; data7 @ P8 : BIDIR; data8 @ R6 : BIDIR; data9 @ N5 : BIDIR; data10 @ P5 : BIDIR; data11 @ R4 : BIDIR; data12 @ R2 : BIDIR; data13 @ P1 : BIDIR; data14 @ N3 : BIDIR; data15 @ N1 : BIDIR; % 10-bit PC I/O address bus % addr0 @ P7 : INPUT; addr1 @ F13 : INPUT; addr2 @ E15 : INPUT; addr3 @ D15 : INPUT; addr4 @ N7 : INPUT; addr5 @ N8 : INPUT; addr6 @ R9 : INPUT; addr7 @ P9 : INPUT; addr8 @ N9 : INPUT; addr9 @ R10 : INPUT; /aen @ C6 : INPUT; % address enable % /iow @ N2 : INPUT; % I/O write % /ior @ N11 : INPUT; % I/O read % /iordy @ P12 : OUTPUT; % I/O ready % dmareq3 @ R11 : OUTPUT; % DMA request #3 % /dmaack3 @ P11 : BIDIR; % DMA acknowledge #3 % dmareq7 @ R3 : OUTPUT; % DMA request #7 % /dmaack7 @ R5 : BIDIR; % DMA acknowledge #7 % dmatc @ R8 : BIDIR; % DMA terminal count % intreq7 @ N10 : OUTPUT; % interrupt request #7 % intreq15 @ P6 : OUTPUT; % interrupt request #15 % pcclk @ R15 : BIDIR; % 8 MHz PC clock % sbhe @ R7 : BIDIR; % system bus high enable % /io16 @ N6 : OUTPUT; % 16-bit I/O % % global bus data lines % global00 @ J1 : BIDIR; % array write strobe % global01 @ H2 : BIDIR; % array read strobe % global02 @ H1 : BIDIR; global03 @ G2 : BIDIR; % array /cs % global04 @ G1 : BIDIR; % array D0 % global05 @ F3 : BIDIR; % array D1 % global06 @ F2 : BIDIR; % array D2 % global07 @ F1 : BIDIR; % array D3 % global08 @ E3 : BIDIR; % array D4 % global09 @ E2 : BIDIR; % array D5 % global10 @ E1 : BIDIR; % array D6 % global11 @ D2 : BIDIR; % array D7 % global12 @ D1 : BIDIR; global13 @ C2 : BIDIR; global14 @ C1 : BIDIR; global15 @ B1 : BIDIR; global16 @ B6 : BIDIR; global17 @ A6 : BIDIR; global18 @ C7 : BIDIR; global19 @ B7 : BIDIR; global20 @ A7 : BIDIR; global21 @ C8 : BIDIR; global22 @ B8 : BIDIR; global23 @ A8 : BIDIR; global24 @ C9 : BIDIR; global25 @ B9 : BIDIR; global26 @ A9 : BIDIR; global27 @ C10 : BIDIR; global28 @ B10 : BIDIR; global29 @ A10 : BIDIR; global30 @ C11 : BIDIR; global31 @ B11 : BIDIR; global32 @ A11 : BIDIR; global33 @ B12 : BIDIR; global34 @ A12 : BIDIR; global35 @ B13 : BIDIR; % global bus / external bus controls % /bank_oe1 @ A14 : OUTPUT; bank_out1 @ A13 : OUTPUT; /bank_oe2 @ B15 : OUTPUT; bank_out2 @ B14 : OUTPUT; /bank_oe3 @ C15 : OUTPUT; bank_out3 @ C14 : OUTPUT; /bank_oe4 @ E14 : OUTPUT; bank_out4 @ E13 : OUTPUT; % dedicated external bus signals % extin0 @ G14 : INPUT; extin1 @ F15 : INPUT; extin2 @ F14 : INPUT; extout0 @ J14 : OUTPUT; extout1 @ H15 : OUTPUT; extout2 @ H14 : OUTPUT; extout3 @ G15 : OUTPUT; % array configuration signals % tclk @ P15 : OUTPUT; % JTAG clock % tms @ N14 : OUTPUT; % JTAG mode % rstb @ M14 : OUTPUT; % JTAG reset (active low) % /array_status @ L15 : BIDIR; array_conf_done @ L14 : BIDIR; /array_config @ L13 : OUTPUT; cs1 @ B5 : BIDIR; % chip selects for each 81188 % cs2 @ A4 : BIDIR; % these become TDI for IQ160 % cs3 @ A3 : BIDIR; cs4 @ A2 : BIDIR; cs5 @ M2 : BIDIR; cs6 @ L3 : BIDIR; cs7 @ K3 : BIDIR; cs8 @ K1 : BIDIR; rdy1 @ A5 : BIDIR; % ready lines for each 81188 % rdy2 @ C5 : BIDIR; % these become TDO for IQ160 % rdy3 @ B4 : BIDIR; rdy4 @ B3 : BIDIR; rdy5 @ M1 : BIDIR; rdy6 @ L2 : BIDIR; rdy7 @ K2 : BIDIR; rdy8 @ J2 : BIDIR; % fast bus % fast0 @ K15 : BIDIR; fast1 @ K14 : BIDIR; fast2 @ J15 : BIDIR; fast3 @ D14 : INPUT; % from external bus % % miscellaneous % sclk0 @ P4 : OUTPUT; % sampling clocks for IQ160's % sclk1 @ P3 : OUTPUT; osc @ C3 : INPUT; % on-board oscillator % END; END; SUBDESIGN memintfc ( data[15..0] : BIDIR; addr[9..0] : INPUT; /aen : INPUT; /iow : INPUT; /ior : INPUT; /iordy : OUTPUT; dmareq3 : OUTPUT; /dmaack3 : BIDIR; dmareq7 : OUTPUT; /dmaack7 : BIDIR; dmatc : BIDIR; intreq7 : OUTPUT; intreq15 : OUTPUT; /io16 : OUTPUT; sbhe : BIDIR; global[35..00] : BIDIR; cs[8..1] : BIDIR; rdy[8..1] : BIDIR; /array_status : BIDIR; array_conf_done : BIDIR; /array_config : OUTPUT; /bank_oe[4..1] : OUTPUT; bank_out[4..1] : OUTPUT; ext_out[3..0] : INPUT; ext_in[2..0] : INPUT; fast[3..0] : INPUT; sclk[1..0] : OUTPUT; osc : INPUT; tclk : OUTPUT; tms : OUTPUT; rstb : OUTPUT; ) VARIABLE address[18..0] : DFF; % RAM address register % ram[7..0] : DFF; % RAM select bits % select : SOFT; % selected... % write : SOFT; % ... for writing from ISA bus % read : SOFT; % ... for reading to ISA bus % data_read : SOFT; % RAM read control line % data_write : SOFT; % RAM write control line % BEGIN /array_status = TRI(VCC,GND); array_conf_done = TRI(GND,GND); % don't drive this!!! % /array_config = VCC; % detect when the memory tester is addressed over the ISA bus % select = (addr[9..3]==BASE_ADDRESS) & !/aen; write = select & !/iow; % goes high when written to % read = select & !/ior; % goes high when read from % % the lowest byte of the memory address is stored in this register % address0 = LCELL(data0); address1 = LCELL(data1); address2 = LCELL(data2); address3 = LCELL(data3); address4 = LCELL(data4); address5 = LCELL(data5); address6 = LCELL(data6); address7 = LCELL(data7); address[7..0].clk = !(write & addr[2..0]==H"0"); % the middle byte of the memory address is stored in this register % address8 = LCELL(data0); address9 = LCELL(data1); address10 = LCELL(data2); address11 = LCELL(data3); address12 = LCELL(data4); address13 = LCELL(data5); address14 = LCELL(data6); address15 = LCELL(data7); address[15..8].clk = !(write & addr[2..0]==H"1"); % the upper 3 bits of the memory address are stored in this register % address16 = LCELL(data0); address17 = LCELL(data1); address18 = LCELL(data2); address[18..16].clk = !(write & addr[2..0]==H"2"); % select the RAM chip % ram0 = LCELL(data0); ram1 = LCELL(data1); ram2 = LCELL(data2); ram3 = LCELL(data3); ram4 = LCELL(data4); ram5 = LCELL(data5); ram6 = LCELL(data6); ram7 = LCELL(data7); ram[7..0].clk = !(write & addr[2..0]==H"3"); % pass the memory address over the global bus % global08 = TRI(address0,VCC); global09 = TRI(address1,VCC); global10 = TRI(address2,VCC); global11 = TRI(address3,VCC); global12 = TRI(address4,VCC); global13 = TRI(address5,VCC); global14 = TRI(address6,VCC); global15 = TRI(address7,VCC); global16 = TRI(address8,VCC); global17 = TRI(address9,VCC); global18 = TRI(address10,VCC); global19 = TRI(address11,VCC); global20 = TRI(address12,VCC); global21 = TRI(address13,VCC); global22 = TRI(address14,VCC); global23 = TRI(address15,VCC); global24 = TRI(address16,VCC); global25 = TRI(address17,VCC); global26 = TRI(address18,VCC); % pass the RAM selects to the appropriate sockets % cs1 = TRI(ram0,VCC); cs2 = TRI(ram1,VCC); cs3 = TRI(ram2,VCC); cs4 = TRI(ram3,VCC); cs5 = TRI(ram4,VCC); cs6 = TRI(ram5,VCC); cs7 = TRI(ram6,VCC); cs8 = TRI(ram7,VCC); % write data on the ISA bus to the global bus % data_write = write & addr[2..0]==H"4"; global27 = TRI(LCELL(data_write),VCC); global00 = TRI(LCELL(LCELL(data0)),data_write); global01 = TRI(LCELL(LCELL(data1)),data_write); global02 = TRI(LCELL(LCELL(data2)),data_write); global03 = TRI(LCELL(LCELL(data3)),data_write); global04 = TRI(LCELL(LCELL(data4)),data_write); global05 = TRI(LCELL(LCELL(data5)),data_write); global06 = TRI(LCELL(LCELL(data6)),data_write); global07 = TRI(LCELL(LCELL(data7)),data_write); % read data from the global bus onto the ISA bus % data_read = read & addr[2..0]==H"4"; global28 = TRI(LCELL(data_read),VCC); data0 = TRI(LCELL(LCELL(global00)),data_read); data1 = TRI(LCELL(LCELL(global01)),data_read); data2 = TRI(LCELL(LCELL(global02)),data_read); data3 = TRI(LCELL(LCELL(global03)),data_read); data4 = TRI(LCELL(LCELL(global04)),data_read); data5 = TRI(LCELL(LCELL(global05)),data_read); data6 = TRI(LCELL(LCELL(global06)),data_read); data7 = TRI(LCELL(LCELL(global07)),data_read); % keep the rest of the global bus quiet % global29 = TRI(GND,GND); global30 = TRI(GND,GND); global31 = TRI(GND,GND); global32 = TRI(GND,GND); global33 = TRI(GND,GND); global34 = TRI(GND,GND); global35 = TRI(GND,GND); % keep the upper byte of the ISA data bus quiet % data8 = TRI(GND,GND); data9 = TRI(GND,GND); data10 = TRI(GND,GND); data11 = TRI(GND,GND); data12 = TRI(GND,GND); data13 = TRI(GND,GND); data14 = TRI(GND,GND); data15 = TRI(GND,GND); % keep unused ISA bus signals quiet % /iordy = TRI(GND,GND); dmareq3 = TRI(GND,GND); dmareq7 = TRI(GND,GND); /dmaack3= TRI(GND,GND); /dmaack7= TRI(GND,GND); dmatc = TRI(GND,GND); intreq7 = TRI(GND,GND); intreq15= TRI(GND,GND); /io16 = TRI(GND,GND); sbhe = TRI(GND,GND); % keep unused rdy lines quiet % rdy1 = TRI(GND,GND); rdy2 = TRI(GND,GND); rdy3 = TRI(GND,GND); rdy4 = TRI(GND,GND); rdy5 = TRI(GND,GND); rdy6 = TRI(GND,GND); rdy7 = TRI(GND,GND); rdy8 = TRI(GND,GND); % keep external bus drivers powered down % /bank_oe[4..1] = VCC; bank_out[4..1] = VCC; % keep IQ160 signals powered down % sclk0 = GND; sclk1 = GND; tclk = GND; tms = VCC; rstb = VCC; END;