CHIP blank1 BEGIN DEVICE = EPF81188GC232-3; "|/wr" : BIDIR_PIN = T5 {tdf}; "|/oe" : BIDIR_PIN = T10 {tdf}; "|/cs" : BIDIR_PIN = T12 {tdf}; "|a0" : BIDIR_PIN = U13 {tdf}; "|a1" : BIDIR_PIN = U12 {tdf}; "|a2" : BIDIR_PIN = U11 {tdf}; "|a3" : BIDIR_PIN = U10 {tdf}; "|a4" : BIDIR_PIN = U9 {tdf}; "|a5" : BIDIR_PIN = U8 {tdf}; "|a6" : BIDIR_PIN = U7 {tdf}; "|a7" : BIDIR_PIN = U6 {tdf}; "|a8" : BIDIR_PIN = T7 {tdf}; "|a9" : BIDIR_PIN = T8 {tdf}; "|a10" : BIDIR_PIN = T11 {tdf}; "|a11" : BIDIR_PIN = T9 {tdf}; "|a12" : BIDIR_PIN = U5 {tdf}; "|a13" : BIDIR_PIN = T6 {tdf}; "|a14" : BIDIR_PIN = U4 {tdf}; "|a15" : BIDIR_PIN = T3 {tdf}; "|a16" : BIDIR_PIN = U3 {tdf}; "|a17" : BIDIR_PIN = T4 {tdf}; "|a18" : BIDIR_PIN = U2 {tdf}; "|d0" : BIDIR_PIN = U14 {tdf}; "|d1" : BIDIR_PIN = U15 {tdf}; "|d2" : BIDIR_PIN = U16 {tdf}; "|d3" : BIDIR_PIN = R15 {tdf}; "|d4" : BIDIR_PIN = T16 {tdf}; "|d5" : BIDIR_PIN = T15 {tdf}; "|d6" : BIDIR_PIN = T14 {tdf}; "|d7" : BIDIR_PIN = T13 {tdf}; "|blue00" : BIDIR_PIN = T2 {tdf}; "|blue01" : BIDIR_PIN = R3 {tdf}; "|blue02" : BIDIR_PIN = P4 {tdf}; "|blue03" : BIDIR_PIN = R5 {tdf}; "|blue04" : BIDIR_PIN = P5 {tdf}; "|blue05" : BIDIR_PIN = R6 {tdf}; "|blue06" : BIDIR_PIN = R7 {tdf}; "|blue07" : BIDIR_PIN = R8 {tdf}; "|blue08" : BIDIR_PIN = R9 {tdf}; "|blue09" : BIDIR_PIN = P9 {tdf}; "|blue10" : BIDIR_PIN = R10 {tdf}; "|blue11" : BIDIR_PIN = R11 {tdf}; "|blue12" : BIDIR_PIN = R12 {tdf}; "|blue13" : BIDIR_PIN = R13 {tdf}; "|blue14" : BIDIR_PIN = P13 {tdf}; "|blue15" : BIDIR_PIN = P14 {tdf}; "|yellow00" : BIDIR_PIN = B2 {tdf}; "|yellow01" : BIDIR_PIN = B3 {tdf}; "|yellow02" : BIDIR_PIN = a4 {tdf}; "|yellow03" : BIDIR_PIN = B4 {tdf}; "|yellow04" : BIDIR_PIN = d4 {tdf}; "|yellow05" : BIDIR_PIN = a5 {tdf}; "|yellow06" : BIDIR_PIN = C5 {tdf}; "|yellow07" : BIDIR_PIN = d5 {tdf}; "|yellow08" : BIDIR_PIN = a6 {tdf}; "|yellow09" : BIDIR_PIN = B6 {tdf}; "|yellow10" : BIDIR_PIN = C6 {tdf}; "|yellow11" : BIDIR_PIN = a8 {tdf}; "|yellow12" : BIDIR_PIN = B8 {tdf}; "|yellow13" : BIDIR_PIN = C8 {tdf}; "|yellow14" : BIDIR_PIN = a9 {tdf}; "|yellow15" : BIDIR_PIN = B9 {tdf}; "|yellow16" : BIDIR_PIN = C9 {tdf}; "|yellow17" : BIDIR_PIN = D9 {tdf}; "|yellow18" : BIDIR_PIN = a10 {tdf}; "|yellow19" : BIDIR_PIN = B10 {tdf}; "|yellow20" : BIDIR_PIN = C10 {tdf}; "|yellow21" : BIDIR_PIN = a12 {tdf}; "|yellow22" : BIDIR_PIN = B12 {tdf}; "|yellow23" : BIDIR_PIN = C12 {tdf}; "|yellow24" : BIDIR_PIN = a13 {tdf}; "|yellow25" : BIDIR_PIN = C13 {tdf}; "|yellow26" : BIDIR_PIN = D13 {tdf}; "|yellow27" : BIDIR_PIN = a14 {tdf}; "|yellow28" : BIDIR_PIN = B14 {tdf}; "|yellow29" : BIDIR_PIN = D14 {tdf}; "|yellow30" : BIDIR_PIN = B15 {tdf}; "|yellow31" : BIDIR_PIN = B16 {tdf}; "|green00" : BIDIR_PIN = B17 {tdf}; "|green01" : BIDIR_PIN = C16 {tdf}; "|green02" : BIDIR_PIN = C15 {tdf}; "|green03" : BIDIR_PIN = D17 {tdf}; "|green04" : BIDIR_PIN = D16 {tdf}; "|green05" : BIDIR_PIN = D15 {tdf}; "|green06" : BIDIR_PIN = E17 {tdf}; "|green07" : BIDIR_PIN = F17 {tdf}; "|green08" : BIDIR_PIN = F16 {tdf}; "|green09" : BIDIR_PIN = F15 {tdf}; "|green10" : BIDIR_PIN = G17 {tdf}; "|green11" : BIDIR_PIN = G16 {tdf}; "|green12" : BIDIR_PIN = H17 {tdf}; "|green13" : BIDIR_PIN = H15 {tdf}; "|green14" : BIDIR_PIN = J17 {tdf}; "|green15" : BIDIR_PIN = J16 {tdf}; "|green16" : BIDIR_PIN = J15 {tdf}; "|green17" : BIDIR_PIN = J14 {tdf}; "|green18" : BIDIR_PIN = K17 {tdf}; "|green19" : BIDIR_PIN = K15 {tdf}; "|green20" : BIDIR_PIN = L17 {tdf}; "|green21" : BIDIR_PIN = L16 {tdf}; "|green22" : BIDIR_PIN = M17 {tdf}; "|green23" : BIDIR_PIN = M16 {tdf}; "|green24" : BIDIR_PIN = M15 {tdf}; "|green25" : BIDIR_PIN = M14 {tdf}; "|green26" : BIDIR_PIN = N16 {tdf}; "|green27" : BIDIR_PIN = N15 {tdf}; "|green28" : BIDIR_PIN = P16 {tdf}; "|green29" : BIDIR_PIN = P15 {tdf}; "|green30" : BIDIR_PIN = R16 {tdf}; "|green31" : BIDIR_PIN = T17 {tdf}; "|red00" : BIDIR_PIN = B1 {tdf}; "|red01" : BIDIR_PIN = C2 {tdf}; "|red02" : BIDIR_PIN = C3 {tdf}; "|red03" : BIDIR_PIN = d1 {tdf}; "|red04" : BIDIR_PIN = d2 {tdf}; "|red05" : BIDIR_PIN = d3 {tdf}; "|red06" : BIDIR_PIN = E1 {tdf}; "|red07" : BIDIR_PIN = F1 {tdf}; "|red08" : BIDIR_PIN = F2 {tdf}; "|red09" : BIDIR_PIN = F3 {tdf}; "|red10" : BIDIR_PIN = G1 {tdf}; "|red11" : BIDIR_PIN = G2 {tdf}; "|red12" : BIDIR_PIN = H1 {tdf}; "|red13" : BIDIR_PIN = H3 {tdf}; "|red14" : BIDIR_PIN = J1 {tdf}; "|red15" : BIDIR_PIN = J2 {tdf}; "|red16" : BIDIR_PIN = J3 {tdf}; "|red17" : BIDIR_PIN = J4 {tdf}; "|red18" : BIDIR_PIN = K1 {tdf}; "|red19" : BIDIR_PIN = K3 {tdf}; "|red20" : BIDIR_PIN = L1 {tdf}; "|red21" : BIDIR_PIN = L2 {tdf}; "|red22" : BIDIR_PIN = M1 {tdf}; "|red23" : BIDIR_PIN = M2 {tdf}; "|red24" : BIDIR_PIN = M3 {tdf}; "|red25" : BIDIR_PIN = M4 {tdf}; "|red26" : BIDIR_PIN = N2 {tdf}; "|red27" : BIDIR_PIN = N3 {tdf}; "|red28" : BIDIR_PIN = P2 {tdf}; "|red29" : BIDIR_PIN = P3 {tdf}; "|red30" : BIDIR_PIN = R2 {tdf}; "|red31" : BIDIR_PIN = T1 {tdf}; "|global00" : BIDIR_PIN = P1 {tdf}; "|global01" : BIDIR_PIN = N1 {tdf}; "|global02" : BIDIR_PIN = H2 {tdf}; "|global03" : BIDIR_PIN = E2 {tdf}; "|global04" : BIDIR_PIN = a2 {tdf}; "|global05" : BIDIR_PIN = a3 {tdf}; "|global06" : BIDIR_PIN = B5 {tdf}; "|global07" : BIDIR_PIN = d7 {tdf}; "|global08" : BIDIR_PIN = C7 {tdf}; "|global09" : BIDIR_PIN = B7 {tdf}; "|global10" : BIDIR_PIN = D8 {tdf}; "|global11" : BIDIR_PIN = a7 {tdf}; "|global12" : BIDIR_PIN = D10 {tdf}; "|global13" : BIDIR_PIN = D11 {tdf}; "|global14" : BIDIR_PIN = C11 {tdf}; "|global15" : BIDIR_PIN = B11 {tdf}; "|global16" : BIDIR_PIN = a11 {tdf}; "|global17" : BIDIR_PIN = D12 {tdf}; "|global18" : BIDIR_PIN = B13 {tdf}; "|global19" : BIDIR_PIN = a15 {tdf}; "|global20" : BIDIR_PIN = a16 {tdf}; "|global21" : BIDIR_PIN = a17 {tdf}; "|global22" : BIDIR_PIN = E15 {tdf}; "|global23" : BIDIR_PIN = E16 {tdf}; "|global24" : BIDIR_PIN = F14 {tdf}; "|global25" : BIDIR_PIN = H16 {tdf}; "|global26" : BIDIR_PIN = K16 {tdf}; "|global27" : BIDIR_PIN = N17 {tdf}; "|global28" : BIDIR_PIN = P17 {tdf}; "|global29" : BIDIR_PIN = U17 {tdf}; "|global30" : BIDIR_PIN = P11 {tdf}; "|global31" : BIDIR_PIN = P10 {tdf}; "|global32" : BIDIR_PIN = P8 {tdf}; "|global33" : BIDIR_PIN = P7 {tdf}; "|global34" : BIDIR_PIN = P6 {tdf}; "|global35" : BIDIR_PIN = F4 {tdf}; "|fast0" : INPUT_PIN = C1 {tdf}; "|fast1" : INPUT_PIN = C17 {tdf}; "|fast2" : INPUT_PIN = R1 {tdf}; "|fast3" : INPUT_PIN = R17 {tdf}; "|cs" : BIDIR_PIN = E3 {tdf}; "|rdy" : BIDIR_PIN = K2 {tdf}; END; DEFAULT_DEVICES BEGIN AUTO_DEVICE = "EPF8282LC84"; AUTO_DEVICE = "EPF8282TC100"; AUTO_DEVICE = "EPF8282ALC84"; AUTO_DEVICE = "EPF8282ATC100"; AUTO_DEVICE = "EPF8282VLC84"; AUTO_DEVICE = "EPF8282VTC100"; AUTO_DEVICE = "EPF8452LC84"; AUTO_DEVICE = "EPF8452GC160"; AUTO_DEVICE = "EPF8452QC160"; AUTO_DEVICE = "EPF8452ALC84"; AUTO_DEVICE = "EPF8452AGC160"; AUTO_DEVICE = "EPF8452AQC160"; AUTO_DEVICE = "EPF8636ALC84"; AUTO_DEVICE = "EPF8636AQC160"; AUTO_DEVICE = "EPF8636AGC192"; AUTO_DEVICE = "EPF8636ARC208"; AUTO_DEVICE = "EPF8820GC192"; AUTO_DEVICE = "EPF8820RC208"; AUTO_DEVICE = "EPF8820BC225"; AUTO_DEVICE = "EPF8820AQC160"; AUTO_DEVICE = "EPF8820AGC192"; AUTO_DEVICE = "EPF8820ARC208"; AUTO_DEVICE = "EPF8820ABC225"; AUTO_DEVICE = "EPF81188GC232"; AUTO_DEVICE = "EPF81188RC240"; AUTO_DEVICE = "EPF81188UC225"; AUTO_DEVICE = "EPF81188AQC208"; AUTO_DEVICE = "EPF81188AGC232"; AUTO_DEVICE = "EPF81188ARC240"; AUTO_DEVICE = "EPF81500GC280"; AUTO_DEVICE = "EPF81500RC304"; ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; END; LOGIC_OPTIONS BEGIN END; TIMING_POINT BEGIN TPD = null; TCO = null; TSU = null; FREQUENCY = null; CUT_ALL_BIDIR = ON; CUT_ALL_CLEAR_PRESET = ON; END; PROBES BEGIN END; GLOBAL_PROJECT_DEVICE_OPTIONS BEGIN RESERVED_LCELLS_PERCENT = 0; RESERVED_PINS_PERCENT = 0; SECURITY_BIT = OFF; FLEX8000_USER_CLOCK = OFF; FLEX8000_AUTO_RESTART = OFF; FLEX8000_RELEASE_CLEARS = OFF; FLEX8000_ENABLE_DCLK_OUTPUT = OFF; FLEX8000_DISABLE_TIME_OUT = ON; FLEX8000_CONFIG_SCHEME = PASSIVE_PARALLEL_ASYNCHRONOUS; FLEX8000_ENABLE_JTAG = OFF; FLEX8000_DATA0 = UNRESERVED; FLEX8000_DATA1_TO_DATA7 = UNRESERVED; FLEX8000_nWS_nRS_nCS_CS = UNRESERVED; FLEX8000_RDYnBUSY = UNRESERVED; FLEX8000_RDCLK = UNRESERVED; FLEX8000_SDOUT = UNRESERVED; FLEX8000_ADD0_TO_ADD12 = UNRESERVED; FLEX8000_ADD13 = UNRESERVED; FLEX8000_ADD14 = UNRESERVED; FLEX8000_ADD15 = UNRESERVED; FLEX8000_ADD16 = UNRESERVED; FLEX8000_ADD17 = UNRESERVED; FLEX8000_CLKUSR = UNRESERVED; END; GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS BEGIN MULTI_LEVEL_SYNTHESIS = OFF; AUTO_GLOBAL_CLOCK = OFF; AUTO_GLOBAL_CLEAR = OFF; AUTO_GLOBAL_PRESET = OFF; AUTO_GLOBAL_OE = OFF; AUTO_IO_CELL_REGISTERS = OFF; STYLE = NORMAL; DEVICE_FAMILY = FLEX8000; IGNORE_CLIQUE_ASSIGNMENTS = OFF; IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; IGNORE_TIMING_ASSIGNMENTS = OFF; IGNORE_CHIP_ASSIGNMENTS = OFF; IGNORE_PIN_ASSIGNMENTS = OFF; IGNORE_LC_ASSIGNMENTS = OFF; IGNORE_DEVICE_ASSIGNMENTS = OFF; AUTO_REGISTER_PACKING = OFF; END; COMPILER_PROCESSING_CONFIGURATION BEGIN DESIGN_DOCTOR = "OFF"; DESIGN_DOCTOR_RULES = "EPLD"; FUNCTIONAL_SNF_EXTRACTOR = "OFF"; OPTIMIZE_TIMING_SNF = "OFF"; LINKED_SNF_EXTRACTOR = "OFF"; RPT_FILE_EQUATIONS = "ON"; RPT_FILE_HIERARCHY = "ON"; RPT_FILE_LCELL_INTERCONNECT = "ON"; RPT_FILE_USER_ASSIGNMENTS = "ON"; GENERATE_JEDEC_FILE = "OFF"; GENERATE_AHDL_TDO_FILE = "OFF"; SMART_RECOMPILE = "OFF"; TIMING_SNF_EXTRACTOR = "ON"; END; COMPILER_INTERFACES_CONFIGURATION BEGIN EDIF_NETLIST_WRITER = "OFF"; EDIF_OUTPUT_VERSION = "200"; XNF_EMULATE_TRI_STATE_BUSES = "INTERNAL_LOGIC"; XNF_TRANSLATE_INTERNAL_NODE_NAMES = "ON"; XNF_GENERATE_AHDL_TDX_FILE = "ON"; VERILOG_NETLIST_WRITER = "OFF"; VHDL_NETLIST_WRITER = "OFF"; EDIF_INPUT_LMF1 = "altsyn.lmf"; EDIF_INPUT_LMF2 = "*.lmf"; EDIF_OUTPUT_EDC_FILE = "vwl.edc"; EDIF_INPUT_VCC = "VDD"; EDIF_INPUT_GND = "GND"; EDIF_OUTPUT_VCC = "VCC"; EDIF_OUTPUT_GND = "ground"; EDIF_INPUT_USE_LMF1 = "ON"; EDIF_INPUT_USE_LMF2 = "OFF"; EDIF_OUTPUT_USE_EDC = "OFF"; EDIF_OUTPUT_DELAY_CONSTRUCTS = "ON"; EDIF_OUTPUT_MAP_ILLEGAL_CHAR = "ON"; EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = "ON"; EDIF_OUTPUT_FORCE_0NS_DELAYS = "OFF"; EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = "OFF"; END; CUSTOM_DESIGN_DOCTOR_RULES BEGIN RIPPLE_CLOCKS = ON; GATED_CLOCKS = ON; MULTI_LEVEL_CLOCKS = ON; MULTI_CLOCK_NETWORKS = ON; STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; PRESET_CLEAR_NETWORKS = ON; ASYNCHRONOUS_INPUTS = ON; DELAY_CHAINS = ON; RACE_CONDITIONS = ON; EXPANDER_NETWORKS = ON; MASTER_RESET = OFF; END; SIMULATOR_CONFIGURATION BEGIN USE_DEVICE = OFF; SETUP_HOLD = OFF; CHECK_OUTPUTS = OFF; OSCILLATION = OFF; OSCILLATION_TIME = 0.0ns; GLITCH = OFF; GLITCH_TIME = 0.0ns; SIMULATION_INPUT_FILE = null; START_TIME = 0.0ns; END_TIME = 0.0ns; END; TIMING_ANALYZER_CONFIGURATION BEGIN END; PROGRAMMER_CONFIGURATION BEGIN END; OTHER_CONFIGURATION BEGIN ORIGINAL_MAXPLUS2_VERSION = "5.2"; DEFAULT_9K_EXP_PER_LCELL = "1/2"; EXPLICIT_FAMILY = "0"; COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = 32; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = ON; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = ON; SUBFACTOR_EXTRACTION = ON; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = ON; TURBO_BIT = ON; PARALLEL_EXPANDERS = ON; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 BEGIN CASCADE_CHAIN = AUTO; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = AUTO; CARRY_CHAIN_LENGTH = 32; OPTIMIZE = AREA; MINIMIZATION = FULL; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = ON; REDUCE_LOGIC = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = ON; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = ON; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = ON; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC BEGIN CASCADE_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CARRY_CHAIN_LENGTH = -1; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = ON; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; IO_CELL_REGISTER = OFF; SOFT_BUFFER_INSERTION = OFF; DECOMPOSE_GATES = ON; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = ON; REGISTER_OPTIMIZATION = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 BEGIN CASCADE_CHAIN = MANUAL; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN = MANUAL; CARRY_CHAIN_LENGTH = 32; OPTIMIZE = AREA; MINIMIZATION = PART; SLOW_SLEW_RATE = OFF; XOR_SYNTHESIS = OFF; TURBO_BIT = OFF; PARALLEL_EXPANDERS = OFF; EXPANDER_FACTORING = OFF; SOFT_BUFFER_INSERTION = ON; DECOMPOSE_GATES = OFF; REDUCE_LOGIC = OFF; DUPLICATE_LOGIC_EXTRACTION = OFF; NOT_GATE_PUSH_BACK = ON; REFACTORIZATION = OFF; SUBFACTOR_EXTRACTION = OFF; MULTI_LEVEL_FACTORING = OFF; RESYNTHESIZE_NETWORK = OFF; REGISTER_OPTIMIZATION = OFF; END;