ALTERA RIPP10 Design Page

Compiling VHDL Designs with Synopsys for the Altera RIPP10 FPGA Board

This page shows the steps to take a .vhd file and convert it into a .ttf file that can be downloaded to the RIPP10. It will cover the UNIX setup files, the architecture of the RIPP10 board, design_analyzer, Max+PlusII and the download process.

Table of Contents

  • Setup Files
  • The Altera RIPP10 Board
  • Creating designs for the Altera RIPP10 board
  • Design_analyzer
  • Max+PlusII
  • Downloading
  • RIPP10 Memory Interfaces
  • Other Test Files
  • Updated Files and Information on RIPP10 -- includes VHDL simulation environment

    • Setup Files

    In order to successfully use design_analyzer and maxplus2 the following three files must be in your home directory:
  • maxplus2.ini - Each time you start maxplus2 it will read this file, and each time you exit it, this file will be updated.
  • .synopsys_vss.setup - If you already use synopsys, this file may be nearly identical to the one you already have in your home directory for use with Xilinx parts or whatever. The important point is that all of the proper variables get set to point to the needed libraries.
  • .synopsys_dc.setup - This file is setup specific for compiling to Altera Parts and you will need to place this version in your home directory.
    • You will also need to add the following lines to your .cshrc file. setenv SYNOPSYS /fpga3/cad/synopsys setenv LM_LICENSE_FILE /fpga3/cad/altera/maxplus2/adm/license.altera setenv ALT_HOME /fpga3/cad/altera/maxplus2 source $SYNOPSYS/admin/install/sim/bin/environ.csh Add the following directories to the head of your path: $SYNOPSYS/hp700/syn/bin $SYNOPSYS/hp700/sim/bin $SYNOPSYS/hp700/sge/bin $SYNOPSYS/iview1/bin $ALT_HOME/bin All of the above information for setting up Synopsys for use with MaxPlusII can be found in application note 34 from Altera entitled Synopsys & Max+PlusII Logic Design. The latest version of the app. note is version 5, Jan. 1995.

    The Altera RIPP10 Board

     Picture of the RIPP10 Board

    This picture shows the RIPP10 board populated with two EPF81188GC232-3 FPGAs and three 128K, 8-bit, 70 ns SRAMs. Also shown on the right of the board is the EPF8452GC160-3 FPGA used to interface the board to the ISA bus on the PC. All of the FPGAs are part of the FLEX8000 device family.

    Pins of the 81188 FPGA Pins of the 8452 FPGA Black colored pins are nonassignable. These are views of the FPGAs as if you were holding the FPGA in your hand with the pins facing you and with pin A1 in the bottom left hand corner. Pin A1 is indicated on the FPGA by the dot on the top side of the FPGA. It is indicated on the circuit board by the square pad.

    The following paragraph is somewhat incorrect, but has been left in so that the rest of the tutorial makes sense. There are really four distinct sets of pin assignments for the 81188GC232 FPGAs found on the RIPP10 board. Updated files are provided at the end of this tutorial page. -- PG

    The layout of the RIPP10 board is fairly simple but can be confusing with the lack of proper documentation. The following is an attempt to correct (hence there may still be errors) the problems of the original documentation with pin and device labeling on the board. The original software for the board made a distinction between odd- and even-numbered FPGAs on the RIPP10 board. This would seem fairly straightforward given that the FPGAs are numbered u1-u8 on the board. However, it appears that there was an error in device labeling on the board as the even numbered FPGAs are labeled: u2,u4,u5,u7 while the odd-numbered FPGAs are labeled: u1,u3,u6,u8. Thus, half of the board was labeled incorrectly (in the wrong order). I will still maintain the use of the terms odd and even, however, to refer to the two types of FPGA on the board. The types of FPGA differ only in their pinouts. Thus, there are separate pinout lists for odd-numbered and even-numbered FPGAs.

    Interconnection structure of the RIPP10 board

    RIPP10 bus structure This picture shows the layout of the buses on the RIPP10 board. As can be seen in Figure 1, only the 8452 FPGA is connected to the ISA bus. Thus, all bus interface configurations must be downloaded to the 8452 FPGA. Also, all of the other FPGAs are loaded from the ISA bus through the 8452 FPGA. Thus, to load an 81188 FPGA with a configuration one must first load the 8452 with the appropriate bus interface (possible due to an on board PLD) and then load the 81188 FPGA from the ISA bus through the 8452. The buses on the RIPP10 board are:
  • Global bus : A 36-bit global bus connected to all of the 81188 FPGAs and the 8452 interface FPGA.
  • External buses: 40 bits of external bus connected ot the global bus and the 8452 FPGA.
  • Fast bus: 4-bit fast bus connected to all of the 81188 FPGAs and the 8452 FPGA used mainly for distributing clocks and reset signals.
  • Green buses: Four 32-bit buses which provide connections between U1 and U5, U2 and U6, U3 and U7, U4 and U8.
  • Red buses: Four 32-bit buses which provide connections between U1 and U7, U2 and U8, U3 and U5, U4 and U6.
  • Yellow buses: Four 32-bit buses which provide connections between U1 and U4, U2 and U3, U5 and U8, U6 and U7.
  • Blue buses: Four 46-bit blue buses which provide connections between U1 and U2, U3 and U4, U5 and U6, U7 and U8, and also provide connections to the SRAMs as can be seen in Figure 2. The connections to the SRAMs through the 46-bit Blue bus (blue[45..0]) are.
  • blue[15..0] -- not connected to the RAM
  • blue[34..16] -- address lines[18..0]
  • blue[42..35] -- data lines[7..0]
  • blue[45..43] -- /cs, /oe, /wr respectively

    • Since the RAMs on our RIPP10 board are only 128k they only need 17 address lines, hence A18 and A17 are unneeded. A18 can simply be left tri-stated. However, A17 is, in fact, a ram enable line for the 128k SRAMs and hence should be held high.

    Each RAM is paired with two FPGAs as follows:

  • RAM U9 - FPGAs U1 and U2
  • RAM U10 - FPGAs U3 and U4
  • RAM U11 - FPGAs U5 and U6
  • RAM U12 - FPGAs U7 and U8
    • The RAM can be controlled from either of the two FPGAs to which it is connected. It also can be disabled by pulling its /cs line high and then the remaining 45 lines of the blue bus can be used for 81188 communication.

    Bus pinouts for the FPGAs on the RIPP10 board

    First, the pinout list for the 8452 interface FPGA: 8452-Pinout

    Again, the following paragraph is a bit misleading, but was left so that tutorial itself makes sense. Updated files are provided at the end of this tutorial page. -- PG

    Next, pinouts for the "odd" and "even" FPGAs. Note: the pinouts for the global bus are the same for both the "odd" and "even" numbered FPGAs.

  • "odd" FPGAs (u1,u3,u6,u8) Pinout: Odd-Pinout
  • "even" FPGAs (u2,u4,u5,u7) Pinout: Even-Pinout

    • As can be seen from the 8452 pinout list the board has two clock sources feeding it. These are the approx. 8 MHz PC clock from the ISA bus and a 40 MHz oscillator on the RIPP10 board. These can be fed out over the fast lines as will be shown in the possible 8452 interface chip configurations below.

    8452 interface FPGA configurations

    There are several configurations for the 8452 interface FPGA that are commonly used when using the RIPP10 board. The first of these is the interface needed to load the 81188 FPGAs on the RIPP10 board with the appropriate configuration data. Another common configuration is that used to load and unload the on-board SRAMs with data. This requires the 81188 FPGAs to be loaded with configurations that allow loading and unloading of the SRAMs and the 8452 to be configured to allow communication with these SRAM loading/unloading configurations. Finally, the 8452 can be programmed with custom configurations that allow a user to interact with custom 81188 designs from the ISA bus. An example of this will follow in the tutorial below where a custom 8452 configuration has been created that allows single stepping of the system clock,toggling of a global reset line, and reading of the global bus on the RIPP10 board all from the keyboard on the PC.

    All of the configurations for the 8452 have currently been designed using Altera's hardware description language (AHDL). These are fairly straightforward and should be understandable to anyone having even limited familiarity with the programming of PALS or other devices using design languages. A list of several configurations for the 8452 interface FPGA and 81188 FPGAs follow.

  • ripload5.tdf: 8452 interface used for loading of the 81188 FPGAs from the ISA bus through the 8452 interface FPGA.
  • ripload5.acf: Pin assignment and configuration file for the above 8452 FPGA configuration.
  • memintfc.tdf: 8452 interface used for reading and writing of the memories.
  • mem1.tdf: Odd-numbered 81188 configuration that allows reading and writing to its attached SRAM from the ISA bus.
  • mem2.tdf: Even-numbered 81188 configuration that allows reading and writing to its attached SRAM from the ISA bus.
  • 529int.tdf: 8452 interface created for EE529 class that allows single stepping of system clock, n-step stepping of the system clock, toggling of a master reset line, and reading of the global bus all from the PC keyboard.
  • 529int.acf: Pin assignment and configuration file for the above 8452 FPGA configuration.
  • 529.cpp: C program that allows control of the 529int.tdf interface from the keyboard.
  • 529d.cpp: Modified version of 529.cpp

    • As might be noticed, some of the configuration files have associated with them an assignment and configuration file (.acf file) and some do not. This is because old versions of Max+PlusII allowed pin assignements to be made within the design file (.tdf file) itself while new versions do not. The old style is still compatible, the compiler will simply create a .acf file automatically when given a .tdf file with pin assignment information in it. It will then comment out the pin assignment data in the .tdf file.

    Using the pin lists and configuration files

    Exactly how to use these pinout lists and configuration files with a design to cause the appropriate pin assignments on the board to be made will be discussed in the sections covering the design_analyzer and Max+PlusII below.

    Creating designs for the Altera RIPP10 board

     The following sections will detail how to take a VHDL design, compile it with Synopsys' design_analyzer to an Altera FPGA design, transfer it to Max+PlusII as an EDIF file, compile it with Max+PlusII with the appropriate pin assignments, and download it to the board.

    Design_analyzer

     This portion of the tutorial will analyze count32.vhd so the steps of analyzing can be seen without clouding the issue with a complex design. This file is a simple 32-bit counter with reset. You will know your setup works correctly if you are able to get the same results.

    NOTE: Analyzing files this way is different than using vhdlan and is not compatible with that file format (IE reanalyze all the files that you depend on). Successfully analyzing with vhdlan is no guarantee of success with design_analyzer.

    Explanation of the count32.vhd file:

    Looking at the count32.vhd file you will notice something peculiar that takes some explaining. The entity port declaration contains not only the declarations for the clk, reset, and cnt ports but also has declarations for all of the other unused pins that are otherwise connected on the RIPP10 board. You will notice that the RIPP10 board pins that are not being used in the design are simply declared as inputs. The reason for doing this is as follows: When placing a design onto the RIPP10 board it is desirable that unused pins on a particular FPGA have no effect on the operation of other FPGAs in the design. Ideally the place and route software would place unused pins in a high-impedance state and that would be that. Unfortunately, this does not happen with the current Altera software. Thus, to overcome this problem one needs to specifically declare these pins as either: 1) disabled tri-stated outputs, or 2) inputs. This will cause the unused pins to not interfere with the operation of other FPGAs connected to the same lines. This would be necessary if say, for example, FPGA U1 desired to use the global bus while FPGA U5 did not. The pins connected to the global bus on FPGA U5 would need to be declared as inputs or tri-stated so that FPGA U5 would not interfere with U1's use of the global bus. The reason that the unused pins must have declarations in the VHDL description is that Max+PlusII will not recognize assignments to the pins in the associated .acf file unless their is a corresponding pin name in the design. In other words, the EDIF file that will be output from Synopsys and imported into Max+PlusII must contain declarations for the unused pins. Otherwise, when we make assignments to the pins as inputs in the .acf file Max+PlusII will just ignore them. The reason that the unused pins are declared as inputs is that Synopsys will just optimize them out if they are declared as outputs and nothing is connected to them. The following is a link to VHDL port declarations that can be simply pasted into your VHDL entity port declarations. Then you simply delete the name of the pins you are going to use and you are done. rip_port.vhd

    Using design_analyzer to synthesize the VHDL design:

    From the UNIX prompt, type design_analyzer. If your paths are ok, it should come up. Analyze your .vhd file by selecting File->Analyze.. from the menu and select count32.vhd. The setting of library defaults to WORK which simply means that it will analyze the file into your WORK library. As soon as design_analyzer begins to analyze your file, another window will pop up showing the libraries loaded and any syntax errors it encounters in your file. If successful the return value will show one as follows: 1 design_analyzer> Hit to close the window and then elaborate the file by choosing File->Elaborate.. from the menu. Click on DEFAULT or WORK in the library listing and the design entity and architecture name should appear in the design list. Click on the proper design name in the design list (in this case count32(count32_arch)) and hit OK. Again, you should get a return value of one if everything goes ok. Hit to close the elaboration window.

    At this point you should see an icon or series of icons on the sheet as shown. Click on the icon (or top-level entity icon if more than one appears) and select Tools->Design Optimization... from the menu. This will cause the design optimization menu to come up which allows you so select the mapping effort which I usually set at high. Hit ok and the compilation log window will come up. This is the most time consuming step and if successful will again return a value of one.

    If successful, you will again see the sheet with icons. Double click on the top-entity icon or click on it and hit the down arrow icon. This will show you the first level of your design with the associated ports as shown. Zoom in and you will see that there are ports for every port in your entity declaration. To see the schematic for the counter again push down in the design by double clicking the icon or selecting it and hitting the down arrow icon. This will show you a schematic as shown.

    At this point you can zoom in on selected portions of the schematic and print it out. You can also save to disk (although this could also be done at a higher level). Save the design to an EDIF output file by selecting File->SaveAs.. from the menu. Select EDIF as the output file format and change the filename extension from .db to .edf as shown..

    NOTE: There will be a default shown that will match your entity name, ONLY CHANGE THE EXTENSION .db to .edf and nothing else, maxplus2 has a problem otherwise. ALSO IF YOUR FILE NAME IS TOO LONG, THEN maxplus2 will not do the correct thing and WILL NOT TELL YOU.

    You are now done with the design_analyzer step and are ready to begin using Max+PlusII.

    Max+PlusII

     Start maxplus2 from the UNIX prompt by typing maxplus2. It should take a little longer to bring this up due to the large size of the program.

    First load in the correct file by selecting File->Project Name.. and clicking on the name of the EDIF file created above. (count32.edf)

    NOTE: There have been problems with Max+PlusII loading in an incorrect file (the .vhd file instead of .edf file). If things don't seem to be going right or making sense, try renaming the .vhd file to another name and start over. In other words, sometimes you need to have different names for your .vhd file and your .edf file or Max+PlusII will complain. This is because it will sometimes (for no apparant reason) try and read the .vhd file with its VHDL compiler.

    Select Interfaces->EDIF Netlist Reader Settings and set the vendor to synopsys. Select Assign->Device and set the device to EPF81188GC232-3 in the FLEX8000 device family (you may need to click on show all package speed grades to see this particular part). This is the FPGA found on the RIPP10 board.

    From the Assign Menu choose Global Project Device options.. then FLEX 8000 Device Options.. and make sure the buttons and pull down menu look like this. These options are critical for successful download to the RIPP10 board.

    Now goto the Assign menu and select Global Project Logic Synthesis.... I usually select the automatic global clock option on the first menu. Then select Define Synthesis Style... and set the Carry and Cascade chain options to Manual as shown.. This allows the use of carry and cascade chains as are created by the Synopsys FPGA compiler.

    After you have done this, quit out of Max+PlusII and goto a text editor (this forces a write on the count32.acf file. Find this file (count32.acf) and look at it. You should see the assignment for the device as DEVICE = EPF81188GC232-3 after the first begin. This is where you should insert the pin assignments. These assignments are cnt32pins.txt. As can be seen the clk input is assigned to the fast1 line while the reset input is assigned to the fast2 line. These correspond to the assignments made in the 529int.tdf interface. Note also that the names used in the .acf file correspond to the names used in the .vhd file. The names used for the cnt bus differ slightly however. This is because buses are not currently supported in the version of EDIF that we are using to transfer designs from Synopsys to Max+PlusII. The buses are broken apart as bus_name_0_ for bit zero, bus_name_1_ for bit one, etc... Notice also that the bus pins are declared as outputs and that all of the other unused pins are declared as inputs. The other pin type is BIDIR which is of course used for tri-stateable and bidirectional pins. Your final .acf file should look like count32.acf which has the appropriate assignments for an "odd"-numbered FPGA. This utilizes the pin assignments for an "odd"-numbered FPGA as listed below:

  • rip_pins1.acf - ODD FPGAs
  • rip_pins2.acf - EVEN FPGAs
    • See below for the updated .acf files. -- PG

    If you are looking at the board, the chips are numbered as:

    --------------------- | 4 3 2 1 | | 8 7 6 5 CP | (CP = Smaller control part) -----------| ISA_BUS| ----------

    Now that you have updated the .acf file appropriately you can do the actual placing and routing of the design onto the FPGA. After restarting maxplus2 reload the design (File->Project..) if necessary. To compile the design all you need to do is hit the start button. This design should compile easily but other designs might not. To make the compiler work harder there are options under the Processing->Fitter Settings... menu.

    Upon successful completion, you can look at the rpt file to get information on device usage stats and so forth by double clicking on the rpt icon. To create the .ttf programming file for the counter select File->Combine Programming Files.. and select options so that the selection box looks like this. This will create the .ttf file on disk as count32.ttf. This is simply an ASCII file used to program the FGPA.

    Other options you may wish to try include:

    Downloading

     FTP your .ttf files over to a PC that has a RIPP10 board installed in the lab. Make sure you setup the transfer for ASCII so that the UNIX to PC conversion will be done correctly.

    If you are going to try to do more than one design at a time, try renaming the entity name for each one that you want to do. This is sort of a kludge but it keeps the different designs separate because of the limitations in design_analyzer you can't rename it to anything other than the entity name when doing the save as edif format.

    Downloading to the RIPP10 board consists of the use of several simple programs called aload.exe, iload.exe, and ripreset.exe. iload.exe is used to load the interface FPGA (the 8452) with an appropriate interface configuration while aload.exe is used to load the 81188 FPGAs with configuration data once an appropriate interface has been loaded into the 8452 FPGA. Thus, the programming steps consist of: 1) loading the 8452 with an interface that allows the 81188 FPGAs to be loaded from the ISA bus, 2) loading the 81188 FPGAs with their appropriate interfaces, and 3) loading the 8452 with any new interface needed by the application. The ripreset.exe program is used to initialize the RIPP10 board. Here is the c code for the aload.exe, iload.exe, and ripreset.exeprograms:

  • iload.c - 8452 FPGA
  • aload.c - 81188 FPGAs
  • ripreset.c
    • In addition the following two programs are often useful:
  • poke.c
  • peek.c
    • Two interfaces have been created that are used to load unused 81188 FPGAs with what can be termed a blank configuration. These configurations are used to cause all of the pins of the FPGA to be tri-stated so that they will not interfere with the operation of other FPGAs connected to the same lines. These interfaces are:
  • blank1.tdf - Odd numbered FPGAs u1,u3,u6,u8
  • blank2.tdf - Even numbered FPGAs u2,u4,u5,u7
  • blank1.acf - Pin assignment file for blank1.tdf
  • blank2.acf - Pin assignment file for blank2.tdf
    • Actual downloading of the counter design to the RIPP10 board and testing is fairly easy using the following batch file: count32.bat. This batch file loads the ripload5.tdf ISA bus interface to the 8452, then it loads FPGA u1 with the counter and FPGAs u2,u3,u5, and u6 with appropriate blank configurations. This assumes that there are FPGAs in locations u2,u3,u5, and u6. It then loads the 8452 interface to allow control of the counter and starts the appropriate counter interface program. All of the necessary files and programs for this batch file can be found in the c32test.zip file available by anonymous ftp from itchy.ee.byu.edu in the directory pub/ripp10/rippboard. The necessary files can also be found on the 486's in the lab that have RIPP10 boards attached in the directory c:\ripp10.

    This pretty much concludes the 32-bit counter example. Another example of an application running on the RIPP10 board can be found on the black 486 in the lab in the directory c:\svga. The two demo programs are f3x3.exe and f5x5.exe which are video filters of size 3x3 and 5x5 respectively. The two images available are train and cats. These demos only work on the black computer due to video card constraints and expect that there are 5 81188 FPGAs installed on the RIPP10 board. Also, the networking software must not be loaded for the demos to work properly.

    RIPP10 Memory Interfaces

    In order to allow loading and unloading of memories from/to text files a memory management program called memmang.exe has been created. This consists of two interface files: mem1.ttf and mem2.ttf which are interfaces to the SRAMs to be loaded into FPGAs u1,u3,u5,u7 and u2,u4,u6,u8 respectively. The interface program and its associated files can be found on the ftp site itchy.ee.byu.edu in the directory pub/ripp10/rippboard as the file memmang.zip. The zip file contains a readme explaining more about the use of the program.

    Other Test Files
  • testmem.vhd - 32-bit counter that writes to SRAM as it counts.
  • testmem.acf - 32-bit counter (testmem) pin assignment file for "odd" FPGAs
  • u1.vhd - 32-bit counter that routes its output onto the green bus
  • u1.acf - Pin assignment file for u1.vhd for "odd" FPGAs
  • u5.vhd - Takes green bus as inputs as routes them onto the global bus
  • u5.acf - Pin assignment file for u5.vhd for "even" FPGAs

    • Updated Files and Information on RIPP10

    David Clark created a Splash 2-like VHDL environment for the Altera RIPP10 board. The complete environment and some examples can be downloaded as     ripp10.tgz, a gzip'ed tar file, or simply as ripp10.tar. Also included in the file are the PC tools for executing designs on the Altera RIPP10 board, their associated source code, and some example designs to execute.

    The VHDL entity and architectures for the FPGAs can be found in altparts.vhd. The .acf-style pin list for the 81188GC232 FPGAs in this VHDL model can be retrieved below:

  • pins_u1.acf -- Used for the U1 FPGA
  • pins_u2.acf -- Used for the U2 FPGA
  • pins_u3.acf -- Used for the U3 FPGA
  • pins_u4.acf -- Used for the U4 FPGA
  • pins_u5.acf -- Used for the U5 FPGA
  • pins_u6.acf -- Used for the U6 FPGA
  • pins_u7.acf -- Used for the U7 FPGA
  • pins_u8.acf -- Used for the U8 FPGA
    • Go to the Reconfigurable Logic Lab Home Page
    Created March 14, 1995 by David Clark
    Updated Tue March 14 13:55:22 1995 Updated Wed August 16, 1995 by Russell Petersen

    Last modified: Tue May 28 10:10:48 MDT 1996 by Paul Graham

    Please send comments to: grahamp@fpga.ee.byu.edu