This picture shows the RIPP10 board populated with two EPF81188GC232-3 FPGAs and three 128K, 8-bit, 70 ns SRAMs. Also shown on the right of the board is the EPF8452GC160-3 FPGA used to interface the board to the ISA bus on the PC. All of the FPGAs are part of the FLEX8000 device family.
Pins of the 81188 FPGA Pins of the 8452 FPGA Black colored pins are nonassignable. These are views of the FPGAs as if you were holding the FPGA in your hand with the pins facing you and with pin A1 in the bottom left hand corner. Pin A1 is indicated on the FPGA by the dot on the top side of the FPGA. It is indicated on the circuit board by the square pad.
The following paragraph is somewhat incorrect, but has been left in so that the rest of the tutorial makes sense. There are really four distinct sets of pin assignments for the 81188GC232 FPGAs found on the RIPP10 board. Updated files are provided at the end of this tutorial page. -- PG
The layout of the RIPP10 board is fairly simple but can be confusing with the lack of proper documentation. The following is an attempt to correct (hence there may still be errors) the problems of the original documentation with pin and device labeling on the board. The original software for the board made a distinction between odd- and even-numbered FPGAs on the RIPP10 board. This would seem fairly straightforward given that the FPGAs are numbered u1-u8 on the board. However, it appears that there was an error in device labeling on the board as the even numbered FPGAs are labeled: u2,u4,u5,u7 while the odd-numbered FPGAs are labeled: u1,u3,u6,u8. Thus, half of the board was labeled incorrectly (in the wrong order). I will still maintain the use of the terms odd and even, however, to refer to the two types of FPGA on the board. The types of FPGA differ only in their pinouts. Thus, there are separate pinout lists for odd-numbered and even-numbered FPGAs.
Since the RAMs on our RIPP10 board are only 128k they only need 17 address lines, hence A18 and A17 are unneeded. A18 can simply be left tri-stated. However, A17 is, in fact, a ram enable line for the 128k SRAMs and hence should be held high.
Each RAM is paired with two FPGAs as follows:The RAM can be controlled from either of the two FPGAs to which it is connected. It also can be disabled by pulling its /cs line high and then the remaining 45 lines of the blue bus can be used for 81188 communication.
Again, the following paragraph is a bit misleading, but was left so that tutorial itself makes sense. Updated files are provided at the end of this tutorial page. -- PG
Next, pinouts for the "odd" and "even" FPGAs. Note: the pinouts for the global bus are the same for both the "odd" and "even" numbered FPGAs.
As can be seen from the 8452 pinout list the board has two clock sources feeding it. These are the approx. 8 MHz PC clock from the ISA bus and a 40 MHz oscillator on the RIPP10 board. These can be fed out over the fast lines as will be shown in the possible 8452 interface chip configurations below.
All of the configurations for the 8452 have currently been designed using Altera's hardware description language (AHDL). These are fairly straightforward and should be understandable to anyone having even limited familiarity with the programming of PALS or other devices using design languages. A list of several configurations for the 8452 interface FPGA and 81188 FPGAs follow.
As might be noticed, some of the configuration files have associated with them an assignment and configuration file (.acf file) and some do not. This is because old versions of Max+PlusII allowed pin assignements to be made within the design file (.tdf file) itself while new versions do not. The old style is still compatible, the compiler will simply create a .acf file automatically when given a .tdf file with pin assignment information in it. It will then comment out the pin assignment data in the .tdf file.
NOTE: Analyzing files this way is different than using vhdlan and is not compatible with that file format (IE reanalyze all the files that you depend on). Successfully analyzing with vhdlan is no guarantee of success with design_analyzer.
At this point you should see an icon or series of icons on the sheet as shown. Click on the icon (or top-level entity icon if more than one appears) and select Tools->Design Optimization... from the menu. This will cause the design optimization menu to come up which allows you so select the mapping effort which I usually set at high. Hit ok and the compilation log window will come up. This is the most time consuming step and if successful will again return a value of one.
If successful, you will again see the sheet with icons. Double click on the top-entity icon or click on it and hit the down arrow icon. This will show you the first level of your design with the associated ports as shown. Zoom in and you will see that there are ports for every port in your entity declaration. To see the schematic for the counter again push down in the design by double clicking the icon or selecting it and hitting the down arrow icon. This will show you a schematic as shown.
At this point you can zoom in on selected portions of the schematic and print it out. You can also save to disk (although this could also be done at a higher level). Save the design to an EDIF output file by selecting File->SaveAs.. from the menu. Select EDIF as the output file format and change the filename extension from .db to .edf as shown..
NOTE: There will be a default shown that will match your entity name, ONLY CHANGE THE EXTENSION .db to .edf and nothing else, maxplus2 has a problem otherwise. ALSO IF YOUR FILE NAME IS TOO LONG, THEN maxplus2 will not do the correct thing and WILL NOT TELL YOU.
You are now done with the design_analyzer step and are ready to begin using Max+PlusII.
First load in the correct file by selecting File->Project Name.. and clicking on the name of the EDIF file created above. (count32.edf)
NOTE: There have been problems with Max+PlusII loading in an incorrect file (the .vhd file instead of .edf file). If things don't seem to be going right or making sense, try renaming the .vhd file to another name and start over. In other words, sometimes you need to have different names for your .vhd file and your .edf file or Max+PlusII will complain. This is because it will sometimes (for no apparant reason) try and read the .vhd file with its VHDL compiler.
Select Interfaces->EDIF Netlist Reader Settings and set the vendor to synopsys. Select Assign->Device and set the device to EPF81188GC232-3 in the FLEX8000 device family (you may need to click on show all package speed grades to see this particular part). This is the FPGA found on the RIPP10 board.
From the Assign Menu choose Global Project Device options.. then FLEX 8000 Device Options.. and make sure the buttons and pull down menu look like this. These options are critical for successful download to the RIPP10 board.
Now goto the Assign menu and select Global Project Logic Synthesis.... I usually select the automatic global clock option on the first menu. Then select Define Synthesis Style... and set the Carry and Cascade chain options to Manual as shown.. This allows the use of carry and cascade chains as are created by the Synopsys FPGA compiler.
After you have done this, quit out of Max+PlusII and goto a text editor (this forces a write on the count32.acf file. Find this file (count32.acf) and look at it. You should see the assignment for the device as DEVICE = EPF81188GC232-3 after the first begin. This is where you should insert the pin assignments. These assignments are cnt32pins.txt. As can be seen the clk input is assigned to the fast1 line while the reset input is assigned to the fast2 line. These correspond to the assignments made in the 529int.tdf interface. Note also that the names used in the .acf file correspond to the names used in the .vhd file. The names used for the cnt bus differ slightly however. This is because buses are not currently supported in the version of EDIF that we are using to transfer designs from Synopsys to Max+PlusII. The buses are broken apart as bus_name_0_ for bit zero, bus_name_1_ for bit one, etc... Notice also that the bus pins are declared as outputs and that all of the other unused pins are declared as inputs. The other pin type is BIDIR which is of course used for tri-stateable and bidirectional pins. Your final .acf file should look like count32.acf which has the appropriate assignments for an "odd"-numbered FPGA. This utilizes the pin assignments for an "odd"-numbered FPGA as listed below:See below for the updated .acf files. -- PG
If you are looking at the board, the chips are numbered as:
Now that you have updated the .acf file appropriately you can do the actual placing and routing of the design onto the FPGA. After restarting maxplus2 reload the design (File->Project..) if necessary. To compile the design all you need to do is hit the start button. This design should compile easily but other designs might not. To make the compiler work harder there are options under the Processing->Fitter Settings... menu.
Upon successful completion, you can look at the rpt file to get information on device usage stats and so forth by double clicking on the rpt icon. To create the .ttf programming file for the counter select File->Combine Programming Files.. and select options so that the selection box looks like this. This will create the .ttf file on disk as count32.ttf. This is simply an ASCII file used to program the FGPA.
Other options you may wish to try include:
If you are going to try to do more than one design at a time, try renaming the entity name for each one that you want to do. This is sort of a kludge but it keeps the different designs separate because of the limitations in design_analyzer you can't rename it to anything other than the entity name when doing the save as edif format.
Downloading to the RIPP10 board consists of the use of several simple programs called aload.exe, iload.exe, and ripreset.exe. iload.exe is used to load the interface FPGA (the 8452) with an appropriate interface configuration while aload.exe is used to load the 81188 FPGAs with configuration data once an appropriate interface has been loaded into the 8452 FPGA. Thus, the programming steps consist of: 1) loading the 8452 with an interface that allows the 81188 FPGAs to be loaded from the ISA bus, 2) loading the 81188 FPGAs with their appropriate interfaces, and 3) loading the 8452 with any new interface needed by the application. The ripreset.exe program is used to initialize the RIPP10 board. Here is the c code for the aload.exe, iload.exe, and ripreset.exeprograms:In addition the following two programs are often useful: Two interfaces have been created that are used to load unused 81188 FPGAs with what can be termed a blank configuration. These configurations are used to cause all of the pins of the FPGA to be tri-stated so that they will not interfere with the operation of other FPGAs connected to the same lines. These interfaces are: Actual downloading of the counter design to the RIPP10 board and testing is fairly easy using the following batch file: count32.bat. This batch file loads the ripload5.tdf ISA bus interface to the 8452, then it loads FPGA u1 with the counter and FPGAs u2,u3,u5, and u6 with appropriate blank configurations. This assumes that there are FPGAs in locations u2,u3,u5, and u6. It then loads the 8452 interface to allow control of the counter and starts the appropriate counter interface program. All of the necessary files and programs for this batch file can be found in the c32test.zip file available by anonymous ftp from itchy.ee.byu.edu in the directory pub/ripp10/rippboard. The necessary files can also be found on the 486's in the lab that have RIPP10 boards attached in the directory c:\ripp10.
This pretty much concludes the 32-bit counter example. Another example of an application running on the RIPP10 board can be found on the black 486 in the lab in the directory c:\svga. The two demo programs are f3x3.exe and f5x5.exe which are video filters of size 3x3 and 5x5 respectively. The two images available are train and cats. These demos only work on the black computer due to video card constraints and expect that there are 5 81188 FPGAs installed on the RIPP10 board. Also, the networking software must not be loaded for the demos to work properly.
In order to allow loading and unloading of memories from/to text files a memory management program called memmang.exe has been created. This consists of two interface files: mem1.ttf and mem2.ttf which are interfaces to the SRAMs to be loaded into FPGAs u1,u3,u5,u7 and u2,u4,u6,u8 respectively. The interface program and its associated files can be found on the ftp site itchy.ee.byu.edu in the directory pub/ripp10/rippboard as the file memmang.zip. The zip file contains a readme explaining more about the use of the program.
The VHDL entity and architectures for the FPGAs can be found in altparts.vhd. The .acf-style pin list for the 81188GC232 FPGAs in this VHDL model can be retrieved below:
Last modified: Tue May 28 10:10:48 MDT 1996 by Paul Graham
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