-- MAX+plus II Version 5.0 8/5/94 -- Modified: 11/07/94 20:52:44 -- Dedicated inputs: R1 R17 C1 C17 on 81188 -- 8452 Interface to allow single stepping of system clock, -- n-step stepping of the clock, toggling of a master reset line, -- and reading of the global bus. CONSTANT BASE_ADDRESS = B"11000"; % Base address = 300 Hex % CONSTANT STATUS_ADDRESS = H"03"; CONSTANT JTAG_ADDRESS = H"04"; CONSTANT READ_ADDRESS1 = H"05"; CONSTANT READ_ADDRESS2 = H"0B"; CONSTANT READ_ADDRESS3 = H"0C"; CONSTANT READ_ADDRESS4 = H"0D"; CONSTANT CSTEP_ADDRESS = H"06"; CONSTANT CSTEP_CNTA_ADDRESS = H"08"; % These three addresses are used to % CONSTANT CSTEP_CNTB_ADDRESS = H"09"; % load the clock count register. % CONSTANT CSTEP_CNTC_ADDRESS = H"0E"; CONSTANT CSTEP_CNTENABLE_ADDRESS = H"0A"; % Enable the counter % CONSTANT TEST_RESET_ADDRESS = H"07"; CONSTANT CLK_ENABLE_ADDRESS = H"0F"; SUBDESIGN 529int ( data[15..0] : BIDIR; addr[9..0] : INPUT; pcclk : INPUT; /aen : INPUT; /iow : INPUT; /ior : INPUT; /iordy : BIDIR; dmareq3 : BIDIR; /dmaack3 : BIDIR; dmareq7 : BIDIR; /dmaack7 : BIDIR; dmatc : BIDIR; intreq7 : BIDIR; intreq15 : BIDIR; /io16 : BIDIR; sbhe : BIDIR; global35 : INPUT; global34 : INPUT; global33 : INPUT; global32 : INPUT; global31 : INPUT; global30 : INPUT; global29 : INPUT; global28 : INPUT; global27 : INPUT; global26 : INPUT; global25 : INPUT; global24 : INPUT; global23 : INPUT; global22 : INPUT; global21 : INPUT; global20 : INPUT; global19 : INPUT; global18 : INPUT; global17 : INPUT; global16 : INPUT; global15 : INPUT; global14 : INPUT; global13 : INPUT; global12 : INPUT; global11 : INPUT; global10 : INPUT; global09 : INPUT; global08 : INPUT; global07 : INPUT; global06 : INPUT; global05 : INPUT; global04 : INPUT; global03 : INPUT; global02 : INPUT; global01 : INPUT; global00 : INPUT; fast0 : OUTPUT; fast1 : OUTPUT; fast2 : OUTPUT; cs[8..1] : OUTPUT; rdy[8..1] : INPUT; /array_status : INPUT; array_conf_done : BIDIR; /array_config : OUTPUT; /bank_oe[4..1] : OUTPUT; bank_out[4..1] : OUTPUT; extout[3..0] : OUTPUT; extin[2..0] : INPUT; sclk[1..0] : OUTPUT; osc : INPUT; tclk : OUTPUT; tms : OUTPUT; rstb : OUTPUT; ) VARIABLE reset_reg : DFF; % register used to provide a global reset line % clk_reg : DFF; % register used to provide a single stepped clock % clk_enable : DFF; % register used to provide a gated system clock % clk_count_reg[19..0] : DFF; % 20 bit count used for multi-stepping of the clock % counter[19..0] : DFF; % 20 bit counter used to multi-step the clock. % Counter_Enable : NODE; Count_Enable_reg : DFF; % Counter enable register % select : SOFT; % download circuit selected % write : SOFT; % selected for writing % read : SOFT; % selected for reading % /array_ws : SOFT; /array_rs : SOFT; % reading data from array % /array_cs : SOFT; % global array chip select % read_output1 : SOFT; % Control lines for reading back state % read_output2 : SOFT; read_output3 : SOFT; read_output4 : SOFT; tdata[7..0] : NODE; BEGIN select = (addr[9..5]==BASE_ADDRESS) & !/aen; write = select & !/iow; % goes high when downloader is written to % read = select & !/ior; % goes high when downloader is read from % %Pins not used specifically in this interface % % Thus, simply tie the pins down appropriately: % array_conf_done = TRI(GND,GND); /array_config = VCC; /array_ws = VCC; /array_rs = VCC; /array_cs = GND; cs1 = TRI(GND,GND); cs2 = TRI(GND,GND); cs3 = TRI(GND,GND); cs4 = TRI(GND,GND); cs5 = TRI(GND,GND); cs6 = TRI(GND,GND); cs7 = TRI(GND,GND); cs8 = TRI(GND,GND); tclk = GND; tms = GND; rstb = GND; /iordy = TRI(GND, GND); dmareq3 = TRI(GND, GND); dmareq7 = TRI(GND, GND); /dmaack3= TRI(GND, GND); /dmaack7= TRI(GND, GND); dmatc = TRI(GND, GND); intreq7 = TRI(GND, GND); intreq15= TRI(GND, GND); /io16 = TRI(GND, GND); sbhe = TRI(GND, GND); /bank_oe[4..1] = VCC; bank_out[4..1] = VCC; extout0 = TRI(GND,GND); extout1 = TRI(GND,GND); extout2 = TRI(GND,GND); extout3 = TRI(GND,GND); sclk0 = GND; sclk1 = GND; % End of pins that are not used. % % Provide method of reading global bus output at 305 Hex % read_output1 = read & addr[4..0] == READ_ADDRESS1; % Provide method of reading global bus output at 30B Hex % read_output2 = read & addr[4..0] == READ_ADDRESS2; % Provide method of reading global bus output at 30C Hex % read_output3 = read & addr[4..0] == READ_ADDRESS3; % Provide method of reading global bus output at 30D Hex % read_output4 = read & addr[4..0] == READ_ADDRESS4; IF read_output1 then tdata0 = LCELL(global00); tdata1 = LCELL(global01); tdata2 = LCELL(global02); tdata3 = LCELL(global03); tdata4 = LCELL(global04); tdata5 = LCELL(global05); tdata6 = LCELL(global06); tdata7 = LCELL(global07); elseif read_output2 then tdata0 = LCELL(global08); tdata1 = LCELL(global09); tdata2 = LCELL(global10); tdata3 = LCELL(global11); tdata4 = LCELL(global12); tdata5 = LCELL(global13); tdata6 = LCELL(global14); tdata7 = LCELL(global15); elseif read_output3 then tdata0 = LCELL(global16); tdata1 = LCELL(global17); tdata2 = LCELL(global18); tdata3 = LCELL(global19); tdata4 = LCELL(global20); tdata5 = LCELL(global21); tdata6 = LCELL(global22); tdata7 = LCELL(global23); elseif read_output4 then tdata0 = LCELL(global24); tdata1 = LCELL(global25); tdata2 = LCELL(global26); tdata3 = LCELL(global27); tdata4 = LCELL(global28); tdata5 = LCELL(global29); tdata6 = LCELL(global30); tdata7 = LCELL(global31); else tdata0 = GND; tdata1 = GND; tdata2 = GND; tdata3 = GND; tdata4 = GND; tdata5 = GND; tdata6 = GND; tdata7 = GND; end if; data0 = TRI(tdata0,(read_output1 # read_output2 # read_output3 # read_output4)); data1 = TRI(tdata1,(read_output1 # read_output2 # read_output3 # read_output4)); data2 = TRI(tdata2,(read_output1 # read_output2 # read_output3 # read_output4)); data3 = TRI(tdata3,(read_output1 # read_output2 # read_output3 # read_output4)); data4 = TRI(tdata4,(read_output1 # read_output2 # read_output3 # read_output4)); data5 = TRI(tdata5,(read_output1 # read_output2 # read_output3 # read_output4)); data6 = TRI(tdata6,(read_output1 # read_output2 # read_output3 # read_output4)); data7 = TRI(tdata7,(read_output1 # read_output2 # read_output3 # read_output4)); data8 = TRI(GND,GND); data9 = TRI(GND,GND); data10 = TRI(GND,GND); data11 = TRI(GND,GND); data12 = TRI(GND,GND); data13 = TRI(GND,GND); data14 = TRI(GND,GND); data15 = TRI(GND,GND); % Provide a pin for free running of the pc Clk line % fast0 = LCELL(pcclk); % Now provide a single stepped and multi-stepped clock line % % First allow loading of a count register % clk_count_reg[7..0].clk = !(write & addr[4..0] == CSTEP_CNTA_ADDRESS); clk_count_reg[15..8].clk = !(write & addr[4..0] == CSTEP_CNTB_ADDRESS); clk_count_reg[19..16].clk = !(write & addr[4..0] == CSTEP_CNTC_ADDRESS); clk_count_reg[0].d = LCELL(data0); clk_count_reg[1].d = LCELL(data1); clk_count_reg[2].d = LCELL(data2); clk_count_reg[3].d = LCELL(data3); clk_count_reg[4].d = LCELL(data4); clk_count_reg[5].d = LCELL(data5); clk_count_reg[6].d = LCELL(data6); clk_count_reg[7].d = LCELL(data7); clk_count_reg[8].d = LCELL(data0); clk_count_reg[9].d = LCELL(data1); clk_count_reg[10].d = LCELL(data2); clk_count_reg[11].d = LCELL(data3); clk_count_reg[12].d = LCELL(data4); clk_count_reg[13].d = LCELL(data5); clk_count_reg[14].d = LCELL(data6); clk_count_reg[15].d = LCELL(data7); clk_count_reg[16].d = LCELL(data0); clk_count_reg[17].d = LCELL(data1); clk_count_reg[18].d = LCELL(data2); clk_count_reg[19].d = LCELL(data3); % Provide a way to disable/enable and reset the counter % Count_Enable_reg.clk = !(write & addr[4..0] == CSTEP_CNTENABLE_ADDRESS); Count_Enable_reg.d = LCELL(data0); Counter_Enable = (clk_count_reg[].q != counter[].q) & Count_Enable_reg.q; counter[].clk = pcclk; counter[].clrn = Count_Enable_reg.q; % Clear is low asserted % % Count until the number of counts has expired % if Counter_Enable then counter[].d = counter[].q + 1; else counter[].d = counter[].q; end if; % Provide register to use in single stepping of the clock % clk_reg.clk = !(write & addr[4..0] == CSTEP_ADDRESS); clk_reg.d = LCELL(data0); fast1 = LCELL(clk_reg.q # (Counter_Enable&pcclk) # (clk_enable.q&pcclk)); % Provide gated 8 Mhz clock to allow enabling and disabling of the system clock % clk_enable.clk = !(write & addr[4..0] == CLK_ENABLE_ADDRESS); clk_enable.d = LCELL(data0); % Put in a reset line % reset_reg.clk = !(write & addr[4..0] == TEST_RESET_ADDRESS); reset_reg.d = LCELL(data0); fast2 = LCELL(reset_reg.q); END;