/* Synopsys customization file (jma 11/91) */

  /* Place the path name of your work directory below (instead of mypath) */
define_design_lib WORK -path mypath

company     = "BYU";
designer    = get_unix_variable(USER);
splash_root = get_unix_variable(SPLASH2);
xsi_root = /ti1/xsi

/* Setup for design using Altera Parts with FPGA Compiler */

search_path = {. /fpga3/cad/altera/maxplus2/synopsys/library/alt_syn/flex8000/lib \
		synopsys_root + "/libraries/syn" \
		/ee2/synopsys/packages/dware/lib };

target_library = { flex8000_fpga.db };
synthetic_library = { flex8000_fpga.sldb dw01.sldb dw02.sldb dw03.sldb \
		     dw04.sldb dw05.sldb dw07.sldb };
symbol_library = {altera.sdb generic.sdb };
link_library = { flex8000_fpga.sldb flex8000_fpga.db dw01.sldb \
	dw02.sldb dw03.sldb dw04.sldb dw05.sldb dw07.sldb };
edifout_netlist_only = "true";
edifout_power_and_ground_representation = "net";
edifout_power_net_name = "VDD";
edifout_ground_net_name = "GND";
edifout_no_array = "true";
edifin_power_net_name = "VDD";
edifin_ground_net_name = "GND";

/* Define my working directory */
define_design_lib WORK -path ./WORK

define_design_lib DW_FLEX8000_FPGA -path /fpga3/cad/altera/maxplus2/synopsys/library/alt_syn/flex8000/lib/dw_flex8000_fpga

define_design_lib DWARE -path /ee2/synopsys/packages/dware/lib

/* define_design_lib RIPP10 -path ~/grahamp/src/ripp10/lib */
/* printing and saving info */ 

plot_command              = "lp -d ps425b";