-- Simple sorter cell.  Passes small value out, keeps big value.
-- Brent Nelson 1/30/98
-- Used in conjunction with sort.vhd to build insertion sorter
--   to demonstrate hierarchical compilation.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity sortCell is
  port(clk : in bit;
       clr : in bit;
       din : in unsigned(7 downto 0);
       dout : out unsigned(7 downto 0));
end sortCell;

architecture rtl of sortCell is
  signal sav : unsigned(7 downto 0);
  begin


  -- Compare incoming with saved.  Keep big one.
  process(clk, clr, din, sav)
    begin
    if clk'event and clk = '1' then
      if clr = '1' then
	dout <= (others => '0');
	sav  <= (others => '0');
      elsif (sav < din) then
	sav <= din;
	dout <= sav;
      else
	dout <= din;
      end if;
    end if;
  end process;
end rtl;