-- Insertion sort design.
-- Brent Nelson 1/30/98
-- Used in conjunction with sortCell.vhd to 
--   demonstrate hierarchical compilation.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity sort is
  port(clk : in bit;
       clr : in bit;
       din : in unsigned(7 downto 0);
       dout : out unsigned(7 downto 0));
end sort;

architecture rtl of sort is
  constant len : integer := 8;
  type pipe is array(0 to len) of unsigned(7 downto 0);
  signal stages : pipe;

  component sortCell
    port(clk : in bit;
         clr : in bit;
         din : in unsigned(7 downto 0);
         dout : out unsigned(7 downto 0));
  end component;
--  for all:sortCell use entity WORK.sortCell(rtl);
    
  begin

  -- Input
  stages(0) <= din;

  GG: for i in 0 to len-1 generate
    G: sortCell port map(clk, clr, stages(i), stages(i+1));
    end generate;

  -- Output
  dout <= stages(len);

end rtl;