/**********************************************************************/
/* File: dc_2_sort.cmd
   Purpose: Demonstration of hierarchical compilation using SYNOPSYS.
            Version #2 - using set_dont_touch to handle multiple instances
*/ 

/* Clean everything out */
remove_design -designs


/* Read and elaborate just the sortCell (read will do here) */
read -f vhdl { sortCell.vhd }

/* Now compile sortCell */
/* Use design compiler, NOT FPGA compiler */
/* If running interactively, choose "Tools->Design Optimization" */

compile

/* Tell SYNOPSYS to leave this alone - it is "done" */
set_dont_touch sortCell true

/* Now read in and compile sort */
read -f vhdl  sort.vhd

/* See how there is only one copy of sortCell? */

/* Save all the .db files for later use */
write -hierarchy

/* We now have to flatten the hierarchy before writing out a netlist */

/* First, tell SYNOPSYS to let us flatten this cell */
set_dont_touch sortCell false


/* The rest of this is specific to writing TERAMAC netlists out.  You */
/* may ignore if you are not using TERAMAC. */

/* Now write out a flat verilog netlist file */
ungroup -all -flatten
write -f verilog -output sort.ver