BYU Configurable Computing Laboratory Projects
BYU Configurable Computing Laboratory Projects
Since its creation in 1993, the BYU Configurable Computing Laboratory
has completed many projects on the custom computing machines in the
lab. This list summarizes the work over the last few years.
Current Projects
Linux on FPGA's
- Focus of Attention Processing
for Automatic Target Recognition
- Sonar Beamforming using
employing FPGAs, DSPs, and general-purpose processors
- CAD Tool support for Run-time
Reconfigurable systems and Domain-Specific Compilation
Previous Masters Thesis'
Automatic Target Recognition
using pre-compiled control structures (Richard Ross)
- Automatic Target Recognition
on SPLASH and Teramac (Mike Rencher)
- SPLASH Parallel Genetic
Algorithm (SPGA) (Paul Graham)
- Supporting FPGA Microprocessors
Through Retargetable Software Tools (Dave Clark)
- Run-Time Reconfigurable Neural
Network 2- RRANN2 (Jim Hadley)
- Mixing DSP with
Reconfigurable Logic (Russ Peterson)
- Systolic Approach for Solving
Systems of Linear Equations (Cameron McNairy)
- Run-Time Reconfigurable Neural
Network 1- RRANN1 (Jim Eldredge)
- Stochastic Neural Network
(Stephen Bade)
Senior Projects
- FPGA Microprocessor (Justin Diether)
- Real-Time Video averaging
filter (Richard Ross)
- RLL Encoder (DISC Module)
- Tactile Sensing (Charles Graham)
Other Projects
- Bit-Serial Automatic Target
Recognition (Justin Diether, Mike Wirthlin, and Peter Bellows)
- The Dynamic Instruction Set Computer (DISC)
Class Projects
- On-Board System logic analyzers
- Hough Transform Engine
- FIR Filter
- Simulated Annealing Simulator
- Ray Tracing Algorithm
- Encryption/Decryption Engine
- Cache Simulation Performance Analyser
- Graphics Co-procesor
The following list displays each custom computing machine and the
projects developed for it.
Teramac
- Genetic Sequence Comparator
- Automatic Target Recognition
SPLASH
- Parallel Genetic Algorithm
- Image Processing Filters
- Systolic Approach for Solving Systems of Linear Equations
- Token Based Data-Flow Machine
RIPP10
- Image Processing Filters
- Conway's Game of Life Simulator
- Board Level VHDL Models
Xilinx Prototyping Board
ClayFun Board
- Dynamic Instruction Set Processor (DISC)
ClaySDK
- Run-Time Reconfigurable Neural Network 2 (CLAy based)
Giga-Ops Spectrum Board
MSI ACE-12
- Run-Time Reconfigurable Neural Network
- On-Board System logic analyzers (aids debugging other applications)
- Hough Transform Engine
- FIR Filter
- Simulated Annealing Simulator
- Ray Tracing Algorithm
- Encryption/Decryption Engine
- Cache Simulation Performance Analyser
- Graphics Co-procesor
- DMA Based Signed Digit Arithmetic Co-Processor
Other
- Run-Time Reconfigurable Tactile Sensor Processor
- Stochastic Neural Network
- Real Time Performance Evaluation - Processor Context Switching Monitor
Go to the Configurable Computing Lab Home Page
Last modified: May 24, 2005