BYU RLL Grad. Student: James Hadley

Reconfigurable Logic Lab Former Graduate Student

James D. Hadley

Jim graduated from BYU in August, 1995. His research focused on run-time reconfiguration (RTR), partially reconfigurable systems, and partially reconfigurable design methodology. His thesis is titled "The Performance Enhancement of a Run-Time Reconfigurable FPGA System Through Partial Reconfiguration".

Jim currently works for Intel Corporation and lives in Oregon.

Designing a partially reconfigured system: J.D. Hadley, B. L. Hutchings. "Designing a partially reconfigured system," in Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, John Schewel, Editor, Proc. SPIE 2607, pp. 210-220 (1995).
Design Methodologies for Partially Reconfigured Systems: J. D. Hadley, B. L. Hutchings. "Design Methodologies for Partially Reconfigured Systems", In Peter Athanas and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 78-84, Los Alamitos, California, April 1995. IEEE Computer Society, IEEE Computer Society Press.

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Last Modified: 12 April, 1996

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