Brigham Young University Configurable Computing Lab

JHDL Osiris Board Model

Compiling the Osiris Board Model

1. Make sure that you have all of the osiris directory (jhdl/platforms/osiris) checked out.
2. Execute the following at the command line from your jhdl directory: ant boardmodel -Dmodel=osiris [-Dskip.xmac=1]

Creating Your Own Osiris Design

1. To begin constructing your circuit, you will want to do one of two things, either open up /jhdl/platforms/osiris/ blank_user.java to use as a guide file, or simply copy it into your working directory and rename it to whatever name you want your circuit called. Most of the code is pretty self-explanatory and there are plenty of comments to help you correctly construct your design. The only modifications that should be made will come after the connect calls; you must use the port names provided. Just be sure that all of the signals that are being explicitly driven in blank_user.java
   (eg. gnd_o(fifoa_re)) remain driven by something when you are ready to simulate or netlist.
2. If you desire to use UserRegisters in your design be sure to uncomment the import statement that is provided near the top of the file. Then all you need to do is follow the instructions provided in the register section and drive the dataOut with 32 bits of whatever your circuit requires.
3. If you wish to netlist, you must uncomment the getCellName() method at the bottom of the file. This will allow your circuit to be renamed as osiris_netlistable_part so that the edif will be compatible with the vhdl edif.
4. There is something that you must be aware of when using the SDRAM. You must take into careful consideration the sdram_busy signal. If you attempt to read from or write to the SDRAM while the busy signal is asserted, your requested transaction will be ignored. The busy signal is asserted whenever the system is accessing the SDRAM or whenver it is being refreshed. You must monitor the sdram_busy signal to effectively use the SDRAM.
5. Here are some example circuits that illustrate how to use specific elements:   Fifo Example, Register Example, Memory Example, SDRAM Example.
6. Now, all you need to do is compile (i.e. jikes yourDesign.java).

Osiris Simulation

1. Once the Osiris board model and your user design are compiled, you can then simulate the circuit, using JL(Jab Lite). You do this by simply executing the following at the command line:   java Osiris yourDesign
2. Your circuit should now be loaded and ready for action. Type help at the JL command line to view all of the Osiris commands that you will need to communicate with your circuit.

Netlisting Your Design

1. Again, make sure that the getCellName() method in your user design is uncommented and returns the string 'osiris_netlistable_part'.
2. Enter the following at the command line:   java Osiris yourDesign --netlist
   You should now have a .edn file and a .rbsym file (for readback purposes). You're now ready to run your design through the tools.

Running Your Design through the Tools

1. Copy /cad/osiris/osiris_latest.tgz to whatever directory you wish to work in. Execute the following:   tar xvfz osiris_latest.tgz
   This should create a netlist directory that contains a makefile, two constraint files, and a vhdl .edf file.
2. Copy your .edn file into the netlist directory as 'osiris_netlistable_part.edf'
3. Make sure that wine is set up in your environment, for help with this go to our Wine setup link.
4. Now, just run make in the netlist directory and if all goes well you will have successfully created an osiris_chip.bit file.

Running Your Design in Hardware Mode

1. Once you have created an osiris_chip.bit file, either copy it to the directory in which your user design class file was created or make sure your classpath points to your user design class file. In either case, osiris_chip.bit must be renamed as Osiris.bit
2. You must set the LD_LIBRARY_PATH environment variable to point to your jhdl/platforms/osiris/hci dirctory. This is where the Osiris JNI plug is located.
3. You should be ready to run your design in hardware. Log on to bludger (the OsirisBoard host) and execute the following in the directory that contains the Osiris.bit file:   java Osiris yourDesign
   Again, type help to see the available osiris commands(see Known Hardware Issues); typing configure will get you up and running in hardware mode. It's all yours from there, enjoy.

Known Hardware Issues

1. A problem arises when accessing the user registers in hardware mode while the clock is not free running. The ctrl_we signal is never asserted in this instance and therefore the data never gets written to the specified register. It works fine, however, when the clock is free running. It is not yet clear whether or not this will be fixed in near-future releases.
2. Another known bug occurs when accessing memory with the clock stopped. In this case, upon accesssing memory, the clock is automatically set to free run whether you want it or not. This, we have been informed, will be fixed in the next release(1.1.2).

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