These pages walk you through the technology mapping hooks in JHDL, and how they are used to target XC4000 designs.  JHDL provides a framework for building up typical FPGA-ish circuits and controlling such FPGA-ish properties as placement and "CLB-packing", all with a syntax / style that is largely independent of the specific device you want to target.  This device-independent interface is the Logic class.  To begin with, we'll talk about the features of the Logic class.  Next, we'll show how the Logic class lets us build up circuits in a very few lines of code.  Third, we'll show how to use the Logic class methods for annotation of technology mapping hints (RLOC's for all you Xilinx-centric folk).   Finally, we'll discuss how to use the JHDL hooks into the Xilinx M1 tools -- the XC4000TechMapper and the edif netlister.

If you are already familiar with the Logic class, you can jump straight into sections #3 & #4.

1. Introduction to the Logic class
2. Building circuits via the Logic class
3. Add tech-mapping hints
4. Netlisting and interfacing to the M1 tools

• Logic class API
• XC4000TechMapper documentation
• XC4000 Library Cell Documentation