Links
Schedules & Assignments
- JHDL.org Public Website
- A link to the public JHDL web page.
- Lab Scheduling Page
- Allows each member of the lab to fill out a personal schedule to allow
for simple planning of lab meetings.
- Lab Animals (Internal)
- Directory of members of the lab community.
- Fall 01 Lab Presentation Schedule
- Lab Presentation Schedule for Fall 2001..
- JHDL Bugzilla Bug Page
- To report or query bugs, go here.
Tutorials/How-tos
- Quick intro to JHDL for new users.
- Provides the steps necessary to start using JHDL in all its many-headed glory. Updated November 15, 1999 by Ben Bullough to reflect changes in JHDL.
- * New Lab Member Orientation Updated June
4,
2002
- A quick start guide briefly covering the main FPGA lab topics.
- JHDL Wildforce Models
- Describes the JHDL Wildforce environment and how to use it.
- JHDL SLAAC1 Models
- Describes the JHDL SLAAC1 environment and how to use it.
- CVS setup/tutorial
- A quick-start introduction to CVS and how we use it here in the lab.
- Ant tutorial
- A quick-start introduction to Ant for building java projects, by John Munsch.
- Schematic Glyph Interface Instructions.
- Tells how to customize a JHDL module so it is drawn the way
you want in the schematic viewer.
- Setting up the Xilinx Alliance
Tools under Linux
- A brief explanation of how to setup your Linux/Wine environment
to execute the Xilinx tools. Also, see the public version
(which may be more recently updated).
- Quick start on using the Xilinx tools under Linux(wine)
- A quick reference for running the Xilinx back-end tools to generate a timing
and/or bitstream file from an EDIF netlist.
- JHDL CVS Tree Branches
- How to set up and use the various branches in the JHDL CVS tree.
- * Compiling JHDL
- How to build JHDL using Ant, including setup of your environment.
- * Testing JHDL
- How to run self tests of JHDL using Ant; also, how to create new JHDL tests.
- Using Stimulators
- How to use the byucc.jhdl.apps.Stimulator.Stimulator class to
perform interactive circuit simulation.
- Using DynamicTestBench
- How to use the byucc.jhdl.apps.dtb.DynamicTestBench class to
dynamically load in a circuit without coding up a full TestBench.
- * Using the JHDL Osiris Model
- How to use the Osiris board model both for simulation and hardware mode.
- * NEW! JHDL Release
Process
- All eight steps outlined necessary to create and publish a new JHDL release
Starred(*) entries indicate the use of the standard style sheet
(they
are
prettier)
Documentation
- Locally Mirrored Xilinx
Documentation
- A collection of Xilinx documentation downloaded from Xilinx.
- SLAAC1-V JHDL Model
- A weak attempt to document SLAAC1-V.
- Wildcard JHDL Model
- Beginning documentation for the Wildcard
- The Latest, Updated JHDL Documentation.
- The latest version of the JHDL documentation (in progress).
- Module Generator Standards/Tutorial
- Outlines how to create a module generator and what it should
include if it is included in the byucc.jhdl.modgen package.
- Module Generator Documenting Instructions.
- Tells how to document module generators for inclusion in the library.
- Xilinx Documentation
- Link to local Xilinx documentation.
- New Documentation (Doesn't have a proper home yet)
-
- * Platforms Util
- Describes how to use the byucc.jhdl.platforms.util to create a
simple board model.
- * Board Models in JHDL
- Describes the ideas behind and how to create a board model in JHDL.
- BVFormat
- Describes how to use the byucc.jhdl.util.BVFormat package
to format BVs.
- JHDL New Placement
- Tells how to use the new JHDL Placement Directives and Transformation methods in Logic.
- Logic, XC4000, and Module Generator Documentation
- The current state of the API documentation.
- ViewManager
- Allows access to Jab viewers without instancing Jab.
- WireWatcherListener
- Allows users to watch wire values.
- BV (BitVector) Documentation
- API for BVs, the object for arbitrary width values for use in JHDL.
- Checkpointing Documentation
- A thorough HOW-TO for checkpointing and the Checkpointable interface.
- JHDLOutput Class Documentation
- Getting up and running using the JHDLOuput Class
On its way out
If you think that this stuff needs to stay around and find a home email
the FPGA List.
- JHDL part II: Netlisting & Technology Mapping for XC4000
- Demonstrates using JHDL for targetting XC4K hardware.