This document offers only simple instructions for using the Xilinx tools under Wine. It does not expect you to know anything, and by the time you finish you will still know nearly nothing. It provides a reminder of the simple steps for getting the tools to run without really having to know how they work. This is nice if all you want to do is generate a configuration bit-stream or get some size and area estimates from the tools.
This section discusses the configuration files and environment variables necessary for using Wine
source /mirrors/usr/wine/setup
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Giving the tools some constraints to work with can increase the performance estimates that it creates for your design. Constraint files are completely optional, and the only constraint discussed here is the clock period
.edn
to
.ucf
.ucf
file:
NET c PERIOD = 10.0 ;
followed by a new-line. The semicolon is very important. The parameter after the equals sign (10.0 in this example) is specified in nano-seconds. You can replace it with anything that you would like. The tools will do their best to meet this constraint but if they can't they will fail horribly. Hence, you cannot just specify a very tiny clock period and take the answer from the tools. You must keep reducing the period until the tools cannot meet it and then take the previous best attempt. Fun, eh?!
At this point you can run any of the Xilinx tools that you would like. Several very nice scripts have been written which will run the tools for you and automatically specify the command line parameters. If you are trying very hard to meet some size or speed constraint, you might want to skip these scripts and fiddle with the command line options. Otherwise, they are very good for generating bit-stream ready configuration files and size and area estimates.
Here are a list of scripts and a brief explanation of what they do:
run_virtex file
|
runs the Xilinx tools (edif2ngd, ngdbuild, map, par, trce) on the specified
.edn
file for a v1000-fg680-6 part
|
run_virtex2 file | runs the Xilinx tools (edif2ngd, ngdbuild, map, par, trce) on the specified .edn file for a xc2v1000-5fg456 part
|
run_virtex_slaac file
|
runs the Xilinx tools (edif2ngd, ngdbuild, map, par, trce) on the specified
.edn
file for a xc2v6000ff1152-4 part, the part that is found on the Osiris board.
|
run_generic file part
|
runs the Xilinx tools (edif2ngd, ngdbuild, map, par, trce) on the specified
.edn
file for a user-defined part. See the Xilinx datasheets for the part code format.
It must be in the style (example)
xc2v1000-fg456-5
.
|
.edn extension but that must not be included on the command line. The script automagically inserts the .edn and .ucf suffixes when processing the files. Again, the .ucf file is optional.
After running the tools, it may be interesting to get a timing estimate for your design. To do this, go to the directory listed at the end of the tools' output (it will look like /tmp/xilinx.12345). Run the command
trce -a -v 400 mydesign.par.ncd
This should report the estimated speed that this design can run at. It also generates a file named mydesign.par.twr that lists the design's critical paths, starting with the longest delay.
To bring up your design in FPGA Editor, from the same directory in the previous step execute the command
fpga_editor mydesign.par.ncd
Ignore any warning messages. Unfortunately, the toolbar buttons for the main screen do not work in FPGA Editor, so you have to find menu options, command-line commands, or keystroke shortcuts that do the same thing
To generate a bitstream to load into an FPGA, execute the command
bitgen -w mydesign.par.ncd mydesign.bit
Note that this will not enable readback, and so can not be used for hardware-mode readback in JHDL.