BYU Reconfigurable Logic Lab Papers

Papers and Publications

Below is a list of recent papers published by members of the Reconfigurable Logic Group at BYU. Compressed versions of the papers are available and were prepared with gzip.


    Published Papers

  1. Reconfigurable Computing Application Frameworks
  2. Using Design-Level Scan to Improve Design Observability and Controllability for Functional Verification of FPGAs
  3. An Application-Specific Compiler for High-Speed Binary Image Morphology
  4. Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing
  5. Optimal Finite Field Multipliers for FPGAs
  6. JHDL-An HDL for Reconfigurable Systems
  7. Frequency-Domain Sonar Processing in FPGAs and DSPs
  8. FPGA-based Sonar Processing
  9. Automated Target Recognition on SPLASH 2
  10. Improving Functional Density Through Run-Time Constant Propagation
  11. Supporting FPGA Microprocessors Through Retargetable Software Tools
  12. Genetic Algorithms In Software and In Hardware - A Performance Analysis of Workstation and Custom Computing Machine Implementations
  13. Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs
  14. Sequencing Run-Time Reconfigured Hardware with Software
  15. Designing a partially reconfigured system
  16. DISC: The dynamic instruction set computer
  17. A Hardware Genetic Algorithm for the Traveling Salesman Problem on SPLASH 2
  18. An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing
  19. Implementation Approaches for Reconfigurable Logic Applications
  20. Design Methodologies for Partially Reconfigured Systems
  21. A Dynamic Instruction Set Computer
  22. The Nano Processor: A Low Resource Reconfigurable Processor
  23. Density Enhancement of a Neural Network Using FPGAs and Run-Time Reconfiguration
  24. FPGA-based Stochastic Neural Networks: Implementation
  25. RRANN: The Run-Time Reconfiguration Artificial Neural Network
  26. RRANN: A Hardware Implementation of the Backpropagation Using Reconfigurable FPGAs

    PhD Theses

  27. Logical Hardware Debuggers for FPGA-Based Systems
  28. Improving Functional Density Through Run-time Circuit Reconfiguration

    Masters Theses

  29. Designing, Debugging, and Deploying Configurable Computing Machine-based Applications Using Reconfigurable Computing Application Frameworks
  30. Analysis of Field-programmable Implementations of Constant Coefficient Finite Impulse Response Filters
  31. Using Hardware Context-Switching to Enable a Multitasking Reconfigurable Computer System
  32. Constant Coefficient Multiplication
  33. Improving Design Observability and Controllability for Functional Verification of FPGA-based Circuits Using Design-level Scan Techniques
  34. An FPGA Implementation of ATR Using Embedded RAM for Control
  35. A Comparison of FPGA Platforms Through SAR/ATR Algorithm Implementation
  36. A Description, Analysis, and Comparison of a Hardware and a Software Implementation of the SPLASH Genetic Algorithm for Optimizing Symmetric Traveling Salesman Problems
  37. The Performance Enhancenent of a Run-Time Reconfigurable FPGA System Through Partial Reconfiguration
  38. An Assessment of The Suitability of Reconfigurable Systems For Digital Signal Processing
  39. Supporting FPGA Microprocessors Through Retargetable Software Tools
  40. FPGA Density Enhancement of a Neural Network Through Run-Time Reconfiguration

    Technical Reports

  41. Improving the FPGA Design Process Through Determining and Applying Logical-to-Physical Design Mappings
  42. FPGAs and DSPs for Sonar Processing --- Inner Loop Computations

Published Papers

Reconfigurable Computing Application Frameworks (pdf-82 K)

Anthony L. Slade, Brent Nelson, Brad Hutchings

"Reconfigurable Computing Application Frameworks", in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2003.

Using Design-Level Scan to Improve Design Observability and Controllability for Functional Verification of FPGAs (pdf-122 K)

Timothy Wheeler, Paul Graham, Brent Nelson, Brad Hutchings

"Using Design-Level Scan to Improve Design Observability and Controllability for Functional Verification of FPGAs", in Proceedings of the Eleventh International Workshop on Field Programmable Logic and Applications, August 2001.

An Application-Specific Compiler for High-Speed Binary Image Morphology (pdf-125 K)

K. Scott Hemmert, Brad L. Hutchings, Anshul Malvi

"An Application-Specific Compiler for High-Speed Binary Image Morphology", in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 2001.

Reconfigurable Processors for High-Performance Embedded Digital Signal Processing (pdf-95 K)

Paul Graham, Brent Nelson

"Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing", in Proceedings of the Ninth International Workshop on Field Programmable Logic and Applications, August 1999.

Optimal Finite Field Multipliers for FPGAs (pdf-95 K)

Captain Gregory Alhquist, Brent Nelson, Michael Rice,

"Optimal Finite Field Multipliers for FPGAs", in Proceedings of the Ninth International Workshop on Field Programmable Logic and Applications, August 1999.

A CAD Suite for High-Performance FPGA Design (pdf-176 K)

Brad Hutchings Peter Bellows, Joseph Hawkins, Scott Hemmert, Brent Nelson, and Mike Rytting

"A CAD Suite for High-Performance FPGA Design", in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 1999.

JHDL-An HDL for Reconfigurable Systems (127 K) (gzip-39 K) (pdf-96 K)

Peter Bellows, Brad Hutchings

"JHDL-An HDL for Reconfigurable Systems", in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 1998.

Frequency-Domain Sonar Processing in FPGAs and DSPs (83 K) (pdf-33 K)

Paul Graham, Brent Nelson

"Frequency-Domain Sonar Processing in FPGAs and DSPs", in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines , April 1998.

FPGA-based Sonar Processing (203 K) (gzip-64 K) (pdf-120 K)

Paul Graham, Brent Nelson

"FPGA-based Sonar Processing", in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, , February 1998,pp. 201-208.

Automated Target Recognition on SPLASH 2 (219 K) (gzip-64 K)

Michael Rencher, B. L. Hutchings

"Automated Target Recognition on SPLASH 2", in Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, April 1997.

Improving Functional Density Through Run-Time Constant Propagation (820K) (gzip-140K)

M. J. Wirthlin, B. L. Hutchings

"Improving Functional Density Through Run-Time Constant Propagation", in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 86-92 (1997).

Supporting FPGA Microprocessors Through Retargetable Software Tools (161K) (gzip-48K)

D. A. Clark, B. L. Hutchings

"Supporting FPGA Microprocessors Through Retargetable Software Tools". In Jeffrey Arnold and Kenneth L. Pocek, editors, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pages 195-203, Los Alamitos, California, April 1996. IEEE Computer Society, IEEE Computer Society Press.

Genetic Algorithms In Software and In Hardware - A Performance Analysis of Workstation and Custom Computing Machine Implementations (194K) (gzip-57K)

P. Graham, B. Nelson.

"Genetic Algorithms In Software and In Hardware - A Performance Analysis of Workstation and Custom Computing Machine Implementations". In Jeffrey Arnold and Kenneth L. Pocek, editors, Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pages 216-225, Los Alamitos, California, April 1996. IEEE Computer Society, IEEE Computer Society Press.

Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs (705K) (gzip-153K)

J.G. Eldredge and B.L. Hutchings.

"Run-Time Reconfiguration: A Method for Enhancing the Functional Density of SRAM-Based FPGAs", in Journal of VLSI Signal Processing, Volume 12, 1996. Pages 67-86

Sequencing Run-Time Reconfigured Hardware with Software (457K) (gzip-106K)

M.J. Wirthlin, B. L. Hutchings.

"Sequencing Run-Time Reconfigured Hardware with Software," in ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pp. 122-128 (1996).

Designing a partially reconfigured system (950K) (gzip-195K)

J.D. Hadley, B. L. Hutchings.

"Designing a partially reconfigured system," in Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, John Schewel, Editor, Proc. SPIE 2607, pp. 210-220 (1995).

DISC: The dynamic instruction set computer (527K) (gzip-108K)

M.J. Wirthlin, B. L. Hutchings.

"DISC: The dynamic instruction set computer", in Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, John Schewel, Editor, Proc. SPIE 2607, pp. 92-103 (1995).

A Hardware Genetic Algorithm for the Traveling Salesman Problem on SPLASH 2 (195K) (gzip-51K)

P. Graham, B. Nelson.

"A Hardware Genetic Algorithm for the Traveling Salesman Problem on SPLASH 2", In 5th International Workshop on Field Programmable Logic and Applications, pp 352-361, August 1995, Oxford, England.

An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing (gzip-42K)

R. Petersen, B. L. Hutchings.

"An Assessment of the Suitability of FPGA-Based Systems for Use in Digital Signal Processing", In 5th International Workshop on Field Programmable Logic and Applications, pp 293-302, August 1995, Oxford, England.

Implementation Approaches for Reconfigurable Logic Applications (gzip-381K)

B. L. Hutchings, M.J. Wirthlin.

"Implementation Approaches for Reconfigurable Logic Applications", In 5th International Workshop on Field Programmable Logic and Applications, pp 419-428, August 1995, Oxford, England.

Design Methodologies for Partially Reconfigured Systems (1686K) (gzip-311K)

J. D. Hadley, B. L. Hutchings. "Design Methodologies for Partially Reconfigured Systems", In Peter Athanas and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 78-84, Los Alamitos, California, April 1995. IEEE Computer Society, IEEE Computer Society Press.

A Dynamic Instruction Set Computer (593K) (gzip-122 K)

M.J. Wirthlin, B. L. Hutchings. In Peter Athanas and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 99 - 107, Los Alamitos, California, April 1995. IEEE Computer Society, IEEE Computer Society Press.

The Nano Processor: A Low Resource Reconfigurable Processor (406K) (gzip-86K)

M.J. Wirthlin, K.L. Gilson, B.L. Hutchings. The Nano Processor: A Low Resource Reconfigurable Processor. In Duncan A. Buell and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 23-30, Los Alamitos, California, April 1994. IEEE Computer Society, IEEE Computer Society Press.

Density Enhancement of a Neural Network Using FPGAs and Run-Time Reconfiguration (530K) (gzip-100K)

J.G. Eldredge and B.L. Hutchings. Density Enhancement of a Neural Network Using FPGAs and Run-Time Reconfiguration. In Duncan A. Buell and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 180-188, Los Alamitos, California, April 1994. IEEE Computer Society, IEEE Computer Society Press.

FPGA-based Stochastic Neural Networks: Implementation (628K) (gzip-132K)

S.L. Bade and B.L. Hutchings. FPGA-based Stochastic Neural Networks: Implementation. In Duncan A. Buell and Kenneth L. Pocek, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 189-198, Los Alamitos, California, April 1994. IEEE Computer Society, IEEE Computer Society Press.

RRANN: The Run-Time Reconfiguration Artificial Neural Network (300K) (gzip-65K)

J.G. Eldredge and B.L. Hutchings. RRANN: The Run-Time Reconfiguration Artificial Neural Network. Custom Integrated Circuits Conference, pages 77-80, San Diego, California, May 1994.

RRANN: A Hardware Implementation of the Backpropagation Using Reconfigurable FPGAs (340K) (gzip-66K)

J.G. Eldredge and B.L. Hutchings. RRANN: A Hardware Implementation of the Backpropagation Using Reconfigurable FPGAs. IEEE World Conference on Computational Intelligence, pages 77-80, Orlando, Florida, June 1994.

PhD Theses

Logical Hardware Debuggers for FPGA-Based Systems (pdf)

Paul Graham, PhD Thesis, Brigham Young University, Electrical and Computer Engineering Department, December 2001.

Improving Functional Density Through Run-time Circuit Reconfiguration (4.1 M) (gzip-1.2 M)

Michael J. Wirthlin, PhD Thesis, Brigham Young University, Electrical and Computer Engineering Department, 1997.

Masters Theses

Designing, Debugging, and Deploying Configurable Computing Machine-based Applications Using Reconfigurable Computing Application Frameworks PDF only, 1.0 MB

Anthony L. Slade, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, April 2003.

Analysis of Field-programmable Implementations of Constant Coefficient Finite Impulse Response Filters PDF only, 717 KB

Benjamin L. Bullough, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, August 2002.

Using Hardware Context-Switching to Enable a Multitasking Reconfigurable Computer System PDF only, 794 KB

Wesley J. Landaker, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, August 2002.

Constant Coefficient Multiplication PDF only, 505 KB

Russel Brian Frederickson, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, December 2001.

Improving Design Observability and Controllability for Functional Verification of FPGA-based Circuits Using Design-level Scan Techniques PDF only, 318 KB

Timothy Brian Wheeler, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, February 2001.

An FPGA Implementation of ATR Using Embedded RAM for Control (2115 K) (gzip-339 K) (pdf)

Richard D. Ross, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, 1997.

A Comparison of FPGA Platforms Through SAR/ATR Algorithm Implementation (785 K) (gzip-215 K)

Michael A. Rencher, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, 1996.

A Description, Analysis, and Comparison of a Hardware and a Software Implementation of the SPLASH Genetic Algorithm for Optimizing Symmetric Traveling Salesman Problems (3558 K) (gzip-709 K)

Paul S. Graham, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, 1996.

The Performance Enhancenent of a Run-Time Reconfigurable FPGA System Through Partial Reconfiguration (574 K) (gzip-116 K)

J.D. Hadley, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, 1995.

An Assessment of The Suitability of Reconfigurable Systems For Digital Signal Processing (883 K) (gzip-205 K)

R. J. Peterson, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, 1995.

Supporting FPGA Mircoprocessors Through Retargetable Software Tools (532 K) (gzip-151 K)

D. A. Clark, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, 1995.

FPGA Density Enhancement of a Neural Network Through Run-Time Reconfiguration (494 K) (gzip-111 K)

James G. Eldredge, Masters Thesis, Brigham Young University, Electrical and Computer Engineering Department, 1994.

Technical Reports

bullet CCL-2000-GHN-1 Improving the FPGA Design Process Through Determining and Applying Logical-to-Physical Design Mappings (ps) (pdf)

Paul Graham, Brad Hutchings, and Brent Nelson, Brigham Young University, 2000

bullet CCL-1998-GN-1 FPGAs and DSPs for Sonar Processing---Inner Loop Computations (342 K) (gzip-118 K)

Paul Graham and Brent Nelson, Brigham Young University, 1998


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Last modified: Tue Apr 22 13:03:35 MDT 2001