Introduction

Run-time reconfiguration (RTR) is an implementation approach which divides an application into a series of sequentially executed stages, with each stage implemented as a separate execution module. Partial RTR extends this approach by partitioning these stages into finer-grain sub-modules which are constructed to be swapped into the platform as needed to contribute towards a given computation. RTR adds dimensions and processing capabilities to configurable computing machinery, which would otherwise simply function as ASIC emulators.

Research Objectives

The investigators propose to develop new programming models, environments, and application interfaces which directly support the development and debugging of RTR applications. The development of an RTR programming model is essential for the advancement of configurable computing systems. A new RTR-based programming model will not only facilitate the programming of RTR systems, but will also heavily influence the future organization of these systems. In addition, run-time kernels, run-time support, RTR debugging tools and other associated tools will result from this research.
 
RTR offers a unique opportunity to reexamine many of the organizational assumptions of programming and computation. Unlike conventional computers, the functionality and organization of RTR systems are allowed to change dynamically as a function of the data. RTR systems will require new programming approaches that are based on advances in high-level task scheduling, temporal partitioning and the implementation of fine-grained operators. The overall objective of this program is to develop a systematic approach to the design, construction, and programming of partial RTR reconfigurable computing systems. All research will be driven by specific DARPA applications as defined by current challenge-problem statements. The following contributions will be made through research performed under this project:

1. A means of achieving higher effective computational density on configurable computing platforms through temporal sharing of the computational resources. This is achieved through an integral set of task development software, and run-time hardware / software for dynamic resource scheduling.

2. A structured approach (and application development tool set) for the creation of run-time reconfigurable applications. The approach proposed is platform-independent, supports design reuse, and provides a means of retargeting through architecture description files.

3. A methodology which directly supports system scalability and platform reuse. Contemporary state-of-the-art RTR platforms will be utilized in this research, yet the results will be extendible to future, more advanced platforms.

BYU is collaborating with Sandia National Laboratories for ATR applications while Virginia Tech is establishing a foundation of a variety of applications including communications, image processing and understanding.

Recent Accomplishments

• Developed a general strategy for cost-effectively accelerating the Focus-of-Attention problem used in Sandia ATR applications. The proposed approach allows a straightforward tradeoff between performance and cost: acceleration rates of 10x to 100x are possible depending on overall system cost. The current approach has been simulated and validated against Sandia's implementation.

• Developed two different RTR implementations of the Chunky-SLD ATR indexer developed at Sandia. Both achieve significant cost-performance advances over previous approaches (10x) . One is based on the Xilinx 6200 fine-grained Reconfigurable Processing Unit (RPU), and the other is based on the Altera 10K CPLD.

• Developed an approach for quantitatively analyzing the costs and benefits of RTR solutions. This model allows RTR implementation styles to be quantitatively compared with their static counterparts allowing a designer or, ultimately, a CAD tool to tradeoff various implementation styles in search of one that meets the required cost-performance. This model was presented at FPGA97.

• Developed two versions of a RTR implementation of a 4x image interpolator using a 2-5-2 B-spline compaction technique. This application is representative of a class of functions which are well-suited for RTR, and exhibits large speed-ups.

• Characterization of RTR processes. To date, most CCMs have relied upon commercial FPGAs -- devices not intended for computation. Devices are emerging which are better suited for computation (most of these devices are being developed under the ACS program). Most of these devices support partial run-time reconfiguration, yet all have unique models for reconfiguration. It is intended that the techniques and tools developed under this program be applicable to a wide diversity of run-time reconfigurable environments. 

Future Plans

• Develop preliminary tools for automatically mapping and partitioning the ATR-FOA application to RTR platforms.

• Further analyze Chunky-SLD (ATR) template databases to further determine what can be exploited to achieve higher performance at lower overall cost (where cost includes: board space, power, actual cost, etc.).

• Develop a first-generation RTR FPGA platform that will be used to early algorithm mapping experiments.

• Develop preliminary RTR overlay library and algorithm analysis tools. 

Further Information

A pdf version of a powerpoint research overview presentation is available. The Configurable Computing Lab at BYU is an additional resource.

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Please send comments to: hutch@ee.byu.edu